MnemonicBrief
| ABS | Absolute value (predicated) |
| ABS | Absolute value |
| ABS | Absolute value (vector) |
| ADC | Add with carry |
| ADCLB | Add with carry long (bottom) |
| ADCLT | Add with carry long (top) |
| ADCS | Add with carry, setting flags |
| ADD (array accumulators) | Add multi-vector to ZA array vector accumulators |
| ADD (array results, multiple and single vector) | Add replicated single vector to multi-vector with ZA array vector results |
| ADD (array results, multiple vectors) | Add multi-vector to multi-vector with ZA array vector results |
| ADD (extended register) | Add extended and scaled register |
| ADD (immediate) | Add immediate value |
| ADD (immediate) | Add immediate (unpredicated) |
| ADD (shifted register) | Add optionally-shifted register |
| ADD (to vector) | Add replicated single vector to multi-vector with multi-vector result |
| ADD (vector) | Add (vector) |
| ADD (vectors, predicated) | Add vectors (predicated) |
| ADD (vectors, unpredicated) | Add vectors (unpredicated) |
| ADDG | Add with tag |
| ADDHA | Add horizontally vector elements to ZA tile |
| ADDHN, ADDHN2 | Add returning high narrow |
| ADDHNB | Add narrow high part (bottom) |
| ADDHNT | Add narrow high part (top) |
| ADDP | Add pairwise |
| ADDP (scalar) | Add pair of elements (scalar) |
| ADDP (vector) | Add pairwise (vector) |
| ADDPL | Add multiple of predicate register size to scalar register |
| ADDPT | Add checked pointer |
| ADDPT (predicated) | Add checked pointer vectors (predicated) |
| ADDPT (unpredicated) | Add checked pointer vectors (unpredicated) |
| ADDQV | Add reduction of quadword vector segments |
| ADDS (extended register) | Add extended and scaled register, setting flags |
| ADDS (immediate) | Add immediate value, setting flags |
| ADDS (shifted register) | Add optionally-shifted register, setting flags |
| ADDSPL | Add multiple of Streaming SVE predicate register size to scalar register |
| ADDSVL | Add multiple of Streaming SVE vector register size to scalar register |
| ADDV | Add across vector |
| ADDVA | Add vertically vector elements to ZA tile |
| ADDVL | Add multiple of vector register size to scalar register |
| ADR | Form PC-relative address |
| ADR | Compute vector address |
| ADRP | Form PC-relative address to 4KB page |
| AESD | AES single round decryption |
| AESD (indexed) | Multi-vector AES single round decryption |
| AESD (vectors) | AES single round decryption |
| AESDIMC | Multi-vector AES single round decryption and inverse mix columns |
| AESE | AES single round encryption |
| AESE (indexed) | Multi-vector AES single round encryption |
| AESE (vectors) | AES single round encryption |
| AESEMC | Multi-vector AES single round encryption and mix columns |
| AESIMC | AES inverse mix columns |
| AESIMC | AES inverse mix columns |
| AESMC | AES mix columns |
| AESMC | AES mix columns |
| AND (immediate) | Bitwise AND with immediate (unpredicated) |
| AND (immediate) | Bitwise AND (immediate) |
| AND (predicates) | Bitwise AND predicates |
| AND (shifted register) | Bitwise AND (shifted register) |
| AND (vector) | Bitwise AND (vector) |
| AND (vectors, predicated) | Bitwise AND vectors (predicated) |
| AND (vectors, unpredicated) | Bitwise AND vectors (unpredicated) |
| ANDQV | Bitwise AND reduction of quadword vector segments |
| ANDS | Bitwise AND predicates, setting the condition flags |
| ANDS (immediate) | Bitwise AND (immediate), setting flags |
| ANDS (shifted register) | Bitwise AND (shifted register), setting flags |
| ANDV | Bitwise AND reduction to scalar |
| APAS | Associate physical address space |
| ASR (immediate) | Arithmetic shift right (immediate) |
| ASR (immediate, predicated) | Arithmetic shift right by immediate (predicated) |
| ASR (immediate, unpredicated) | Arithmetic shift right by immediate (unpredicated) |
| ASR (register) | Arithmetic shift right (register) |
| ASR (vectors) | Arithmetic shift right by vector (predicated) |
| ASR (wide elements, predicated) | Arithmetic shift right by 64-bit wide elements (predicated) |
| ASR (wide elements, unpredicated) | Arithmetic shift right by 64-bit wide elements (unpredicated) |
| ASRD | Arithmetic shift right for divide by immediate (predicated) |
| ASRR | Reversed arithmetic shift right by vector (predicated) |
| ASRV | Arithmetic shift right variable |
| AT | Address translate |
| AUTDA, AUTDZA | Authenticate data address, using key A |
| AUTDB, AUTDZB | Authenticate data address, using key B |
| AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA | Authenticate instruction address, using key A |
| AUTIA171615 | Authenticate instruction address, using key A |
| AUTIASPPC | Authenticate return address using key A, using an immediate offset |
| AUTIASPPCR | Authenticate return address using key A, using a register |
| AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB | Authenticate instruction address, using key B |
| AUTIB171615 | Authenticate instruction address, using key B |
| AUTIBSPPC | Authenticate return address using key B, using an immediate offset |
| AUTIBSPPCR | Authenticate return address using key B, using a register |
| AXFLAG | Convert floating-point condition flags from Arm to external format |
| B | Branch |
| B.cond | Branch conditionally |
| BC.cond | Branch consistent conditionally |
| BCAX | Bit clear and exclusive-OR |
| BCAX | Bitwise clear and exclusive-OR |
| BDEP | Scatter lower bits into positions selected by bitmask |
| BEXT | Gather lower bits from positions selected by bitmask |
| BF1CVT, BF2CVT | Multi-vector convert from 8-bit floating-point to BFloat16 (in-order) |
| BF1CVT, BF2CVT | 8-bit floating-point convert to BFloat16 |
| BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 | 8-bit floating-point convert to BFloat16 (vector) |
| BF1CVTL, BF2CVTL | Multi-vector convert from 8-bit floating-point to deinterleaved BFloat16 |
| BF1CVTLT, BF2CVTLT | 8-bit floating-point convert to BFloat16 (top) |
| BFADD | BFloat16 add multi-vector to ZA array vector accumulators |
| BFADD (predicated) | BFloat16 add vectors (predicated) |
| BFADD (unpredicated) | BFloat16 add vectors (unpredicated) |
| BFC | Bitfield clear |
| BFCLAMP | Multi-vector BFloat16 clamp to minimum/maximum number |
| BFCLAMP | BFloat16 clamp to minimum/maximum number |
| BFCVT | Single-precision down convert to BFloat16 format (predicated) |
| BFCVT | Floating-point convert from single-precision to BFloat16 format (scalar) |
| BFCVT (BFloat16 to 8-bit floating-point) | Multi-vector convert from BFloat16 to packed 8-bit floating-point format |
| BFCVT (single-precision to BFloat16) | Multi-vector convert from single-precision to packed BFloat16 format |
| BFCVTN | Multi-vector convert from single-precision to interleaved BFloat16 format |
| BFCVTN | BFloat16 convert, narrow and interleave to 8-bit floating-point |
| BFCVTN, BFCVTN2 | Floating-point convert from single-precision to BFloat16 format (vector) |
| BFCVTNT | Single-precision down convert and narrow to BFloat16 (top, predicated) |
| BFDOT (by element) | BFloat16 floating-point dot product (vector, by element) |
| BFDOT (indexed) | BFloat16 indexed dot product to single-precision |
| BFDOT (multiple and indexed vector) | Multi-vector BFloat16 dot-product by indexed element |
| BFDOT (multiple and single vector) | Multi-vector BFloat16 dot-product by vector |
| BFDOT (multiple vectors) | Multi-vector BFloat16 dot-product |
| BFDOT (vector) | BFloat16 floating-point dot product (vector) |
| BFDOT (vectors) | BFloat16 dot product to single-precision |
| BFI | Bitfield insert |
| BFM | Bitfield move |
| BFMAX | BFloat16 maximum (predicated) |
| BFMAX (multiple and single vector) | Multi-vector BFloat16 maximum by vector |
| BFMAX (multiple vectors) | Multi-vector BFloat16 maximum |
| BFMAXNM | BFloat16 maximum number (predicated) |
| BFMAXNM (multiple and single vector) | Multi-vector BFloat16 maximum number by vector |
| BFMAXNM (multiple vectors) | Multi-vector BFloat16 maximum number |
| BFMIN | BFloat16 minimum (predicated) |
| BFMIN (multiple and single vector) | Multi-vector BFloat16 minimum by vector |
| BFMIN (multiple vectors) | Multi-vector BFloat16 minimum |
| BFMINNM | BFloat16 minimum number (predicated) |
| BFMINNM (multiple and single vector) | Multi-vector BFloat16 minimum number by vector |
| BFMINNM (multiple vectors) | Multi-vector BFloat16 minimum number |
| BFMLA (indexed) | BFloat16 fused multiply-add vectors by indexed elements |
| BFMLA (multiple and indexed vector) | Multi-vector BFloat16 fused multiply-add by indexed element |
| BFMLA (multiple and single vector) | Multi-vector BFloat16 fused multiply-add by vector |
| BFMLA (multiple vectors) | Multi-vector BFloat16 fused multiply-add |
| BFMLA (vectors) | BFloat16 fused multiply-add vectors |
| BFMLAL (multiple and indexed vector) | Multi-vector BFloat16 multiply-add long by indexed element |
| BFMLAL (multiple and single vector) | Multi-vector BFloat16 multiply-add long by vector |
| BFMLAL (multiple vectors) | Multi-vector BFloat16 multiply-add long |
| BFMLALB (indexed) | BFloat16 multiply-add long to single-precision (bottom, indexed) |
| BFMLALB (vectors) | BFloat16 multiply-add long to single-precision (bottom) |
| BFMLALB, BFMLALT (by element) | BFloat16 floating-point widening multiply-add long (by element) |
| BFMLALB, BFMLALT (vector) | BFloat16 floating-point widening multiply-add long (vector) |
| BFMLALT (indexed) | BFloat16 multiply-add long to single-precision (top, indexed) |
| BFMLALT (vectors) | BFloat16 multiply-add long to single-precision (top) |
| BFMLS (indexed) | BFloat16 fused multiply-subtract vectors by indexed elements |
| BFMLS (multiple and indexed vector) | Multi-vector BFloat16 fused multiply-subtract by indexed element |
| BFMLS (multiple and single vector) | Multi-vector BFloat16 fused multiply-subtract by vector |
| BFMLS (multiple vectors) | Multi-vector BFloat16 fused multiply-subtract |
| BFMLS (vectors) | BFloat16 fused multiply-subtract vectors |
| BFMLSL (multiple and indexed vector) | Multi-vector BFloat16 multiply-subtract long by indexed element |
| BFMLSL (multiple and single vector) | Multi-vector BFloat16 multiply-subtract long by vector |
| BFMLSL (multiple vectors) | Multi-vector BFloat16 multiply-subtract long |
| BFMLSLB (indexed) | BFloat16 multiply-subtract long from single-precision (bottom, indexed) |
| BFMLSLB (vectors) | BFloat16 multiply-subtract long from single-precision (bottom) |
| BFMLSLT (indexed) | BFloat16 multiply-subtract long from single-precision (top, indexed) |
| BFMLSLT (vectors) | BFloat16 multiply-subtract long from single-precision (top) |
| BFMMLA (widening) | BFloat16 matrix multiply-accumulate to single-precision |
| BFMMLA (widening) | BFloat16 matrix multiply-accumulate to single-precision |
| BFMOP4A (non-widening) | BFloat16 quarter-tile outer products, accumulating |
| BFMOP4A (widening) | BFloat16 quarter-tile sums of two outer products, accumulating |
| BFMOP4S (non-widening) | BFloat16 quarter-tile outer products, subtracting |
| BFMOP4S (widening) | BFloat16 quarter-tile sums of two outer products, subtracting |
| BFMOPA (non-widening) | BFloat16 outer product and accumulate |
| BFMOPA (widening) | BFloat16 sum of outer products and accumulate |
| BFMOPS (non-widening) | BFloat16 outer product and subtract |
| BFMOPS (widening) | BFloat16 sum of outer products and subtract |
| BFMUL (indexed) | BFloat16 multiply vectors by indexed elements |
| BFMUL (multiple and single vector) | Multi-vector BFloat16 multiply by vector |
| BFMUL (multiple vectors) | Multi-vector BFloat16 multiply |
| BFMUL (vectors, predicated) | BFloat16 multiply vectors (predicated) |
| BFMUL (vectors, unpredicated) | BFloat16 multiply vectors (unpredicated) |
| BFSCALE | BFloat16 adjust exponent by vector (predicated) |
| BFSCALE (multiple and single vector) | Multi-vector BFloat16 adjust exponent by vector |
| BFSCALE (multiple vectors) | Multi-vector BFloat16 adjust exponent |
| BFSUB | BFloat16 subtract multi-vector from ZA array vector accumulators |
| BFSUB (predicated) | BFloat16 subtract vectors (predicated) |
| BFSUB (unpredicated) | BFloat16 subtract vectors (unpredicated) |
| BFTMOPA (non-widening) | BFloat16 sparse outer product, accumulating |
| BFTMOPA (widening) | BFloat16 sparse sum of two outer products, accumulating |
| BFVDOT | Multi-vector BFloat16 vertical dot-product by indexed element |
| BFXIL | Bitfield extract and insert at low end |
| BGRP | Group bits to right or left as selected by bitmask |
| BIC (immediate) | Bitwise clear bits using immediate (unpredicated) |
| BIC (predicates) | Bitwise clear predicates |
| BIC (shifted register) | Bitwise bit clear (shifted register) |
| BIC (vector, immediate) | Bitwise bit clear (vector, immediate) |
| BIC (vector, register) | Bitwise bit clear (vector, register) |
| BIC (vectors, predicated) | Bitwise clear vectors (predicated) |
| BIC (vectors, unpredicated) | Bitwise clear vectors (unpredicated) |
| BICS | Bitwise clear predicates, setting the condition flags |
| BICS (shifted register) | Bitwise bit clear (shifted register), setting flags |
| BIF | Bitwise insert if false |
| BIT | Bitwise insert if true |
| BL | Branch with link |
| BLR | Branch with link to register |
| BLRAA, BLRAAZ, BLRAB, BLRABZ | Branch with link to register, with pointer authentication |
| BMOPA | Bitwise exclusive NOR population count outer product and accumulate |
| BMOPS | Bitwise exclusive NOR population count outer product and subtract |
| BR | Branch to register |
| BRAA, BRAAZ, BRAB, BRABZ | Branch to register, with pointer authentication |
| BRB | Branch record buffer |
| BRK | Breakpoint instruction |
| BRKA | Break after first true condition |
| BRKAS | Break after first true condition, setting the condition flags |
| BRKB | Break before first true condition |
| BRKBS | Break before first true condition, setting the condition flags |
| BRKN | Propagate break to next partition |
| BRKNS | Propagate break to next partition, setting the condition flags |
| BRKPA | Break after first true condition, propagating from previous partition |
| BRKPAS | Break after first true condition, propagating from previous partition and setting the condition flags |
| BRKPB | Break before first true condition, propagating from previous partition |
| BRKPBS | Break before first true condition, propagating from previous partition and setting the condition flags |
| BSL | Bitwise select |
| BSL | Bitwise select |
| BSL1N | Bitwise select with first input inverted |
| BSL2N | Bitwise select with second input inverted |
| BTI | Branch target identification |
| CADD | Complex integer add with rotate |
| CAS, CASA, CASAL, CASL | Compare and swap word or doubleword in memory |
| CASB, CASAB, CASALB, CASLB | Compare and swap byte in memory |
| CASH, CASAH, CASALH, CASLH | Compare and swap halfword in memory |
| CASP, CASPA, CASPAL, CASPL | Compare and swap pair of words or doublewords in memory |
| CASPT, CASPAT, CASPALT, CASPLT | Compare and swap pair unprivileged |
| CAST, CASAT, CASALT, CASLT | Compare and swap unprivileged |
| CB (immediate) | Compare register with immediate and branch |
| CB (register) | Compare registers and branch |
| CBB | Compare bytes and branch |
| CBBLE | Compare signed less than or equal bytes and branch |
| CBBLO | Compare unsigned lower than bytes and branch |
| CBBLS | Compare unsigned lower than or equal bytes and branch |
| CBBLT | Compare signed less than bytes and branch |
| CBGE (immediate) | Compare signed greater than or equal immediate and branch |
| CBH | Compare halfwords and branch |
| CBHLE | Compare signed less than or equal halfwords and branch |
| CBHLO | Compare unsigned lower than halfwords and branch |
| CBHLS | Compare unsigned lower than or equal halfwords and branch |
| CBHLT | Compare signed less than halfwords and branch |
| CBHS (immediate) | Compare unsigned greater than or equal immediate and branch |
| CBLE (immediate) | Compare signed less than or equal immediate and branch |
| CBLE (register) | Compare signed less than or equal register and branch |
| CBLO (register) | Compare unsigned lower than register and branch |
| CBLS (immediate) | Compare unsigned lower than or equal immediate and branch |
| CBLS (register) | Compare unsigned lower than or equal register and branch |
| CBLT (register) | Compare signed less than register and branch |
| CBNZ | Compare and branch on nonzero |
| CBZ | Compare and branch on zero |
| CCMN (immediate) | Conditional compare negative (immediate) |
| CCMN (register) | Conditional compare negative (register) |
| CCMP (immediate) | Conditional compare (immediate) |
| CCMP (register) | Conditional compare (register) |
| CDOT (indexed) | Complex integer dot product (indexed) |
| CDOT (vectors) | Complex integer dot product |
| CFINV | Invert carry flag |
| CFP | Control flow prediction restriction by context |
| CHKFEAT | Check feature status |
| CINC | Conditional increment |
| CINV | Conditional invert |
| CLASTA (scalar) | Conditionally extract element after last to general-purpose register |
| CLASTA (SIMD&FP scalar) | Conditionally extract element after last to SIMD&FP scalar register |
| CLASTA (vectors) | Conditionally extract element after last to vector register |
| CLASTB (scalar) | Conditionally extract last element to general-purpose register |
| CLASTB (SIMD&FP scalar) | Conditionally extract last element to SIMD&FP scalar register |
| CLASTB (vectors) | Conditionally extract last element to vector register |
| CLRBHB | Clear branch history |
| CLREX | Clear exclusive |
| CLS | Count leading sign bits (predicated) |
| CLS | Count leading sign bits |
| CLS (vector) | Count leading sign bits (vector) |
| CLZ | Count leading zero bits (predicated) |
| CLZ | Count leading zeros |
| CLZ (vector) | Count leading zero bits (vector) |
| CMEQ (register) | Compare bitwise equal (vector) |
| CMEQ (zero) | Compare bitwise equal to zero (vector) |
| CMGE (register) | Compare signed greater than or equal (vector) |
| CMGE (zero) | Compare signed greater than or equal to zero (vector) |
| CMGT (register) | Compare signed greater than (vector) |
| CMGT (zero) | Compare signed greater than zero (vector) |
| CMHI (register) | Compare unsigned higher (vector) |
| CMHS (register) | Compare unsigned higher or same (vector) |
| CMLA (indexed) | Complex integer multiply-add with rotate (indexed) |
| CMLA (vectors) | Complex integer multiply-add with rotate |
| CMLE (zero) | Compare signed less than or equal to zero (vector) |
| CMLT (zero) | Compare signed less than zero (vector) |
| CMN (extended register) | Compare negative (extended register) |
| CMN (immediate) | Compare negative (immediate) |
| CMN (shifted register) | Compare negative (shifted register) |
| CMP (extended register) | Compare (extended register) |
| CMP (immediate) | Compare (immediate) |
| CMP (shifted register) | Compare (shifted register) |
| CMP (immediate) | Compare vector to immediate |
| CMP (vectors) | Compare vectors |
| CMP (wide elements) | Compare vector to 64-bit wide elements |
| CMPLE (vectors) | Compare signed less than or equal to vector, setting the condition flags |
| CMPLO (vectors) | Compare unsigned lower than vector, setting the condition flags |
| CMPLS (vectors) | Compare unsigned lower or same as vector, setting the condition flags |
| CMPLT (vectors) | Compare signed less than vector, setting the condition flags |
| CMPP | Compare with tag |
| CMTST | Compare bitwise test bits nonzero (vector) |
| CNEG | Conditional negate |
| CNOT | Logically invert boolean condition in vector (predicated) |
| CNT | Population count per byte |
| CNT | Count non-zero bits (predicated) |
| CNT | Count bits |
| CNTB, CNTD, CNTH, CNTW | Set scalar to multiple of predicate constraint element count |
| CNTP (predicate as counter) | Set scalar to count from predicate-as-counter |
| CNTP (predicate) | Set scalar to count of true predicate elements |
| COMPACT | Copy active vector elements to lower-numbered elements |
| COSP | Clear other speculative prediction restriction by context |
| CPP | Cache prefetch prediction restriction by context |
| CPY (immediate, merging) | Copy signed integer immediate to vector elements (merging) |
| CPY (immediate, zeroing) | Copy signed integer immediate to vector elements (zeroing) |
| CPY (scalar) | Copy general-purpose register to vector elements (predicated) |
| CPY (SIMD&FP scalar) | Copy SIMD&FP scalar register to vector elements (predicated) |
| CPYFP, CPYFM, CPYFE | Memory copy forward-only |
| CPYFPN, CPYFMN, CPYFEN | Memory copy forward-only, reads and writes non-temporal |
| CPYFPRN, CPYFMRN, CPYFERN | Memory copy forward-only, reads non-temporal |
| CPYFPRT, CPYFMRT, CPYFERT | Memory copy forward-only, reads unprivileged |
| CPYFPRTN, CPYFMRTN, CPYFERTN | Memory copy forward-only, reads unprivileged, reads and writes non-temporal |
| CPYFPRTRN, CPYFMRTRN, CPYFERTRN | Memory copy forward-only, reads unprivileged and non-temporal |
| CPYFPRTWN, CPYFMRTWN, CPYFERTWN | Memory copy forward-only, reads unprivileged, writes non-temporal |
| CPYFPT, CPYFMT, CPYFET | Memory copy forward-only, reads and writes unprivileged |
| CPYFPTN, CPYFMTN, CPYFETN | Memory copy forward-only, reads and writes unprivileged and non-temporal |
| CPYFPTRN, CPYFMTRN, CPYFETRN | Memory copy forward-only, reads and writes unprivileged, reads non-temporal |
| CPYFPTWN, CPYFMTWN, CPYFETWN | Memory copy forward-only, reads and writes unprivileged, writes non-temporal |
| CPYFPWN, CPYFMWN, CPYFEWN | Memory copy forward-only, writes non-temporal |
| CPYFPWT, CPYFMWT, CPYFEWT | Memory copy forward-only, writes unprivileged |
| CPYFPWTN, CPYFMWTN, CPYFEWTN | Memory copy forward-only, writes unprivileged, reads and writes non-temporal |
| CPYFPWTRN, CPYFMWTRN, CPYFEWTRN | Memory copy forward-only, writes unprivileged, reads non-temporal |
| CPYFPWTWN, CPYFMWTWN, CPYFEWTWN | Memory copy forward-only, writes unprivileged and non-temporal |
| CPYP, CPYM, CPYE | Memory copy |
| CPYPN, CPYMN, CPYEN | Memory copy, reads and writes non-temporal |
| CPYPRN, CPYMRN, CPYERN | Memory copy, reads non-temporal |
| CPYPRT, CPYMRT, CPYERT | Memory copy, reads unprivileged |
| CPYPRTN, CPYMRTN, CPYERTN | Memory copy, reads unprivileged, reads and writes non-temporal |
| CPYPRTRN, CPYMRTRN, CPYERTRN | Memory copy, reads unprivileged and non-temporal |
| CPYPRTWN, CPYMRTWN, CPYERTWN | Memory copy, reads unprivileged, writes non-temporal |
| CPYPT, CPYMT, CPYET | Memory copy, reads and writes unprivileged |
| CPYPTN, CPYMTN, CPYETN | Memory copy, reads and writes unprivileged and non-temporal |
| CPYPTRN, CPYMTRN, CPYETRN | Memory copy, reads and writes unprivileged, reads non-temporal |
| CPYPTWN, CPYMTWN, CPYETWN | Memory copy, reads and writes unprivileged, writes non-temporal |
| CPYPWN, CPYMWN, CPYEWN | Memory copy, writes non-temporal |
| CPYPWT, CPYMWT, CPYEWT | Memory copy, writes unprivileged |
| CPYPWTN, CPYMWTN, CPYEWTN | Memory copy, writes unprivileged, reads and writes non-temporal |
| CPYPWTRN, CPYMWTRN, CPYEWTRN | Memory copy, writes unprivileged, reads non-temporal |
| CPYPWTWN, CPYMWTWN, CPYEWTWN | Memory copy, writes unprivileged and non-temporal |
| CRC32B, CRC32H, CRC32W, CRC32X | CRC32 checksum |
| CRC32CB, CRC32CH, CRC32CW, CRC32CX | CRC32C checksum |
| CSDB | Consumption of speculative data barrier |
| CSEL | Conditional select |
| CSET | Conditional set |
| CSETM | Conditional set mask |
| CSINC | Conditional select increment |
| CSINV | Conditional select invert |
| CSNEG | Conditional select negation |
| CTERMEQ, CTERMNE | Compare and terminate loop |
| CTZ | Count trailing zeros |
| DC | Data cache operation |
| DCPS1 | Debug change PE state to EL1 |
| DCPS2 | Debug change PE state to EL2 |
| DCPS3 | Debug change PE state to EL3 |
| DECB, DECD, DECH, DECW (scalar) | Decrement scalar by multiple of predicate constraint element count |
| DECD, DECH, DECW (vector) | Decrement vector by multiple of predicate constraint element count |
| DECP (scalar) | Decrement scalar by count of true predicate elements |
| DECP (vector) | Decrement vector by count of true predicate elements |
| DGH | Data gathering hint |
| DMB | Data memory barrier |
| DRPS | Debug restore PE state |
| DSB | Data synchronization barrier |
| DUP (element) | Duplicate vector element to vector or scalar |
| DUP (general) | Duplicate general-purpose register to vector |
| DUP (immediate) | Broadcast signed immediate to vector elements (unpredicated) |
| DUP (indexed) | Broadcast indexed element to vector (unpredicated) |
| DUP (scalar) | Broadcast general-purpose register to vector elements (unpredicated) |
| DUPM | Broadcast logical bitmask immediate to vector (unpredicated) |
| DUPQ | Broadcast indexed element within each quadword vector segment (unpredicated) |
| DVP | Data value prediction restriction by context |
| EON | Bitwise exclusive-OR with inverted immediate (unpredicated) |
| EON (shifted register) | Bitwise exclusive-OR NOT (shifted register) |
| EOR (immediate) | Bitwise exclusive-OR (immediate) |
| EOR (immediate) | Bitwise exclusive-OR with immediate (unpredicated) |
| EOR (predicates) | Bitwise exclusive-OR predicates |
| EOR (shifted register) | Bitwise exclusive-OR (shifted register) |
| EOR (vector) | Bitwise exclusive-OR (vector) |
| EOR (vectors, predicated) | Bitwise exclusive-OR vectors (predicated) |
| EOR (vectors, unpredicated) | Bitwise exclusive-OR vectors (unpredicated) |
| EOR3 | Bitwise exclusive-OR of three vectors |
| EOR3 | Three-way exclusive-OR |
| EORBT | Interleaving exclusive-OR (bottom, top) |
| EORQV | Bitwise exclusive-OR reduction of quadword vector segments |
| EORS | Bitwise exclusive-OR predicates, setting the condition flags |
| EORTB | Interleaving exclusive-OR (top, bottom) |
| EORV | Bitwise exclusive-OR reduction to scalar |
| ERET | Exception return |
| ERETAA, ERETAB | Exception return, with pointer authentication |
| ESB | Error synchronization barrier |
| EXPAND | Copy lower-numbered vector elements to active elements |
| EXT | Extract vector from pair of vectors |
| EXT | Extract vector from pair of vectors |
| EXTQ | Extract vector segment from each pair of quadword vector segments |
| EXTR | Extract register |
| F1CVT, F2CVT | 8-bit floating-point convert to half-precision |
| F1CVT, F2CVT | Multi-vector convert from 8-bit floating-point to half-precision (in-order) |
| F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 | 8-bit floating-point convert to half-precision (vector) |
| F1CVTL, F2CVTL | Multi-vector convert from 8-bit floating-point to deinterleaved half-precision |
| F1CVTLT, F2CVTLT | 8-bit floating-point convert to half-precision (top) |
| FABD | Floating-point absolute difference (predicated) |
| FABD | Floating-point absolute difference (vector) |
| FABS | Floating-point absolute value (predicated) |
| FABS (scalar) | Floating-point absolute value (scalar) |
| FABS (vector) | Floating-point absolute value (vector) |
| FAC | Floating-point absolute compare vectors |
| FACGE | Floating-point absolute compare greater than or equal (vector) |
| FACGT | Floating-point absolute compare greater than (vector) |
| FACLE | Floating-point absolute compare less than or equal |
| FACLT | Floating-point absolute compare less than |
| FADD | Floating-point add multi-vector to ZA array vector accumulators |
| FADD (immediate) | Floating-point add immediate (predicated) |
| FADD (scalar) | Floating-point add (scalar) |
| FADD (vector) | Floating-point add (vector) |
| FADD (vectors, predicated) | Floating-point add vector (predicated) |
| FADD (vectors, unpredicated) | Floating-point add vector (unpredicated) |
| FADDA | Floating-point add strictly-ordered reduction, accumulating in scalar |
| FADDP | Floating-point add pairwise |
| FADDP (scalar) | Floating-point add pair of elements (scalar) |
| FADDP (vector) | Floating-point add pairwise (vector) |
| FADDQV | Floating-point add recursive reduction of quadword vector segments |
| FADDV | Floating-point add recursive reduction to scalar |
| FAMAX | Floating-point absolute maximum (predicated) |
| FAMAX | Floating-point absolute maximum |
| FAMAX | Multi-vector floating-point absolute maximum |
| FAMIN | Floating-point absolute minimum |
| FAMIN | Multi-vector floating-point absolute minimum |
| FAMIN | Floating-point absolute minimum (predicated) |
| FCADD | Floating-point complex add |
| FCADD | Floating-point complex add with rotate (predicated) |
| FCCMP | Floating-point conditional quiet compare (scalar) |
| FCCMPE | Floating-point conditional signaling compare (scalar) |
| FCLAMP | Multi-vector floating-point clamp to minimum/maximum number |
| FCLAMP | Floating-point clamp to minimum/maximum number |
| FCM (vectors) | Floating-point compare vectors |
| FCM (zero) | Floating-point compare vector with zero |
| FCMEQ (register) | Floating-point compare equal (vector) |
| FCMEQ (zero) | Floating-point compare equal to zero (vector) |
| FCMGE (register) | Floating-point compare greater than or equal (vector) |
| FCMGE (zero) | Floating-point compare greater than or equal to zero (vector) |
| FCMGT (register) | Floating-point compare greater than (vector) |
| FCMGT (zero) | Floating-point compare greater than zero (vector) |
| FCMLA | Floating-point complex multiply accumulate |
| FCMLA (by element) | Floating-point complex multiply accumulate (by element) |
| FCMLA (indexed) | Floating-point complex multiply-add by indexed values with rotate |
| FCMLA (vectors) | Floating-point complex multiply-add with rotate (predicated) |
| FCMLE (vectors) | Floating-point compare less than or equal to vector |
| FCMLE (zero) | Floating-point compare less than or equal to zero (vector) |
| FCMLT (vectors) | Floating-point compare less than vector |
| FCMLT (zero) | Floating-point compare less than zero (vector) |
| FCMP | Floating-point quiet compare (scalar) |
| FCMPE | Floating-point signaling compare (scalar) |
| FCPY | Copy 8-bit floating-point immediate to vector elements (predicated) |
| FCSEL | Floating-point conditional select (scalar) |
| FCVT | Floating-point convert precision (predicated) |
| FCVT | Floating-point convert precision (scalar) |
| FCVT (narrowing, FP16 to FP8) | Multi-vector convert from half-precision to packed 8-bit floating-point format |
| FCVT (narrowing, FP32 to FP16) | Multi-vector convert from single-precision to packed half-precision |
| FCVT (narrowing, FP32 to FP8) | Multi-vector convert from single-precision to packed 8-bit floating-point format |
| FCVT (widening) | Multi-vector convert from half-precision to single-precision (in-order) |
| FCVTAS (scalar SIMD&FP) | Floating-point convert to signed integer, rounding to nearest with ties to away (scalar SIMD&FP) |
| FCVTAS (scalar) | Floating-point convert to signed integer, rounding to nearest with ties to away (scalar) |
| FCVTAS (vector) | Floating-point convert to signed integer, rounding to nearest with ties to away (vector) |
| FCVTAU (scalar SIMD&FP) | Floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar SIMD&FP) |
| FCVTAU (scalar) | Floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar) |
| FCVTAU (vector) | Floating-point convert to unsigned integer, rounding to nearest with ties to away (vector) |
| FCVTL | Multi-vector convert from half-precision to deinterleaved single-precision |
| FCVTL, FCVTL2 | Floating-point convert to higher precision long (vector) |
| FCVTLT | Floating-point up convert long (top, predicated) |
| FCVTMS (scalar SIMD&FP) | Floating-point convert to signed integer, rounding toward minus infinity (scalar SIMD&FP) |
| FCVTMS (scalar) | Floating-point convert to signed integer, rounding toward minus infinity (scalar) |
| FCVTMS (vector) | Floating-point convert to signed integer, rounding toward minus infinity (vector) |
| FCVTMU (scalar SIMD&FP) | Floating-point convert to unsigned integer, rounding toward minus infinity (scalar SIMD&FP) |
| FCVTMU (scalar) | Floating-point convert to unsigned integer, rounding toward minus infinity (scalar) |
| FCVTMU (vector) | Floating-point convert to unsigned integer, rounding toward minus infinity (vector) |
| FCVTN | Half-precision convert, narrow and interleave to 8-bit floating-point |
| FCVTN (FP32 to FP16) | Multi-vector convert from single-precision to interleaved half-precision |
| FCVTN (FP32 to FP8) | Multi-vector convert from single-precision to interleaved 8-bit floating-point format |
| FCVTN (half-precision to 8-bit floating-point) | Half-precision to 8-bit floating-point convert and narrow (vector) |
| FCVTN, FCVTN2 (double to single-precision, single to half-precision) | Floating-point convert to lower precision narrow (vector) |
| FCVTN, FCVTN2 (single-precision to 8-bit floating-point) | Single-precision to 8-bit floating-point convert and narrow (vector) |
| FCVTNB | Single-precision convert, narrow and interleave to 8-bit floating-point (bottom) |
| FCVTNS (scalar SIMD&FP) | Floating-point convert to signed integer, rounding to nearest with ties to even (scalar SIMD&FP) |
| FCVTNS (scalar) | Floating-point convert to signed integer, rounding to nearest with ties to even (scalar) |
| FCVTNS (vector) | Floating-point convert to signed integer, rounding to nearest with ties to even (vector) |
| FCVTNT (predicated) | Floating-point down convert and narrow (top, predicated) |
| FCVTNT (unpredicated) | Single-precision convert, narrow and interleave to 8-bit floating-point (top) |
| FCVTNU (scalar SIMD&FP) | Floating-point convert to unsigned integer, rounding to nearest with ties to even (scalar SIMD&FP) |
| FCVTNU (scalar) | Floating-point convert to unsigned integer, rounding to nearest with ties to even (scalar) |
| FCVTNU (vector) | Floating-point convert to unsigned integer, rounding to nearest with ties to even (vector) |
| FCVTPS (scalar SIMD&FP) | Floating-point convert to signed integer, rounding toward plus infinity (scalar SIMD&FP) |
| FCVTPS (scalar) | Floating-point convert to signed integer, rounding toward plus infinity (scalar) |
| FCVTPS (vector) | Floating-point convert to signed integer, rounding toward plus infinity (vector) |
| FCVTPU (scalar SIMD&FP) | Floating-point convert to unsigned integer, rounding toward plus infinity (scalar SIMD&FP) |
| FCVTPU (scalar) | Floating-point convert to unsigned integer, rounding toward plus infinity (scalar) |
| FCVTPU (vector) | Floating-point convert to unsigned integer, rounding toward plus infinity (vector) |
| FCVTX | Double-precision down convert to single-precision, rounding to odd (predicated) |
| FCVTXN, FCVTXN2 | Floating-point convert to lower precision narrow, rounding to odd (vector) |
| FCVTXNT | Double-precision down convert to single-precision, rounding to odd (top, predicated) |
| FCVTZS | Floating-point convert to signed integer, rounding toward zero (predicated) |
| FCVTZS | Multi-vector floating-point convert to signed integer, rounding toward zero |
| FCVTZS (scalar SIMD&FP) | Floating-point convert to signed integer, rounding toward zero (scalar SIMD&FP) |
| FCVTZS (scalar, fixed-point) | Floating-point convert to signed fixed-point, rounding toward zero (scalar) |
| FCVTZS (scalar, integer) | Floating-point convert to signed integer, rounding toward zero (scalar) |
| FCVTZS (vector, fixed-point) | Floating-point convert to signed fixed-point, rounding toward zero (vector) |
| FCVTZS (vector, integer) | Floating-point convert to signed integer, rounding toward zero (vector) |
| FCVTZU | Floating-point convert to unsigned integer, rounding toward zero (predicated) |
| FCVTZU | Multi-vector floating-point convert to unsigned integer, rounding toward zero |
| FCVTZU (scalar SIMD&FP) | Floating-point convert to unsigned integer, rounding toward zero (scalar SIMD&FP) |
| FCVTZU (scalar, fixed-point) | Floating-point convert to unsigned fixed-point, rounding toward zero (scalar) |
| FCVTZU (scalar, integer) | Floating-point convert to unsigned integer, rounding toward zero (scalar) |
| FCVTZU (vector, fixed-point) | Floating-point convert to unsigned fixed-point, rounding toward zero (vector) |
| FCVTZU (vector, integer) | Floating-point convert to unsigned integer, rounding toward zero (vector) |
| FDIV | Floating-point divide by vector (predicated) |
| FDIV (scalar) | Floating-point divide (scalar) |
| FDIV (vector) | Floating-point divide (vector) |
| FDIVR | Floating-point reversed divide by vector (predicated) |
| FDOT (2-way, indexed, FP16 to FP32) | Half-precision indexed dot product to single-precision |
| FDOT (2-way, indexed, FP8 to FP16) | 8-bit floating-point indexed dot product to half-precision |
| FDOT (2-way, multiple and indexed vector, FP16 to FP32) | Multi-vector half-precision dot-product by indexed element |
| FDOT (2-way, multiple and indexed vector, FP8 to FP16) | Multi-vector 8-bit floating-point dot-product by indexed element to half-precision |
| FDOT (2-way, multiple and single vector, FP16 to FP32) | Multi-vector half-precision dot-product by vector |
| FDOT (2-way, multiple and single vector, FP8 to FP16) | Multi-vector 8-bit floating-point dot-product by vector to half-precision |
| FDOT (2-way, multiple vectors, FP16 to FP32) | Multi-vector half-precision dot-product |
| FDOT (2-way, multiple vectors, FP8 to FP16) | Multi-vector 8-bit floating-point dot-product to half-precision |
| FDOT (2-way, vectors, FP16 to FP32) | Half-precision dot product to single-precision |
| FDOT (2-way, vectors, FP8 to FP16) | 8-bit floating-point dot product to half-precision |
| FDOT (4-way, indexed) | 8-bit floating-point indexed dot product to single-precision |
| FDOT (4-way, multiple and indexed vector) | Multi-vector 8-bit floating-point dot-product by indexed element to single-precision |
| FDOT (4-way, multiple and single vector) | Multi-vector 8-bit floating-point dot-product by vector to single-precision |
| FDOT (4-way, multiple vectors) | Multi-vector 8-bit floating-point dot-product to single-precision |
| FDOT (4-way, vectors) | 8-bit floating-point dot product to single-precision |
| FDOT (8-bit floating-point to half-precision, by element) | 8-bit floating-point dot product to half-precision (vector, by element) |
| FDOT (8-bit floating-point to half-precision, vector) | 8-bit floating-point dot product to half-precision (vector) |
| FDOT (8-bit floating-point to single-precision, by element) | 8-bit floating-point dot product to single-precision (vector, by element) |
| FDOT (8-bit floating-point to single-precision, vector) | 8-bit floating-point dot product to single-precision (vector) |
| FDUP | Broadcast 8-bit floating-point immediate to vector elements (unpredicated) |
| FEXPA | Floating-point exponential accelerator |
| FIRSTP | Scalar index of first true predicate element (predicated) |
| FJCVTZS | Floating-point Javascript convert to signed fixed-point, rounding toward zero |
| FLOGB | Floating-point base 2 logarithm as integer |
| FMAD | Floating-point fused multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm] |
| FMADD | Floating-point fused multiply-add (scalar) |
| FMAX (immediate) | Floating-point maximum with immediate (predicated) |
| FMAX (multiple and single vector) | Multi-vector floating-point maximum by vector |
| FMAX (multiple vectors) | Multi-vector floating-point maximum |
| FMAX (scalar) | Floating-point maximum (scalar) |
| FMAX (vector) | Floating-point maximum (vector) |
| FMAX (vectors) | Floating-point maximum (predicated) |
| FMAXNM (immediate) | Floating-point maximum number with immediate (predicated) |
| FMAXNM (multiple and single vector) | Multi-vector floating-point maximum number by vector |
| FMAXNM (multiple vectors) | Multi-vector floating-point maximum number |
| FMAXNM (scalar) | Floating-point maximum number (scalar) |
| FMAXNM (vector) | Floating-point maximum number (vector) |
| FMAXNM (vectors) | Floating-point maximum number (predicated) |
| FMAXNMP | Floating-point maximum number pairwise |
| FMAXNMP (scalar) | Floating-point maximum number of pair of elements (scalar) |
| FMAXNMP (vector) | Floating-point maximum number pairwise (vector) |
| FMAXNMQV | Floating-point maximum number recursive reduction of quadword vector segments |
| FMAXNMV | Floating-point maximum number across vector |
| FMAXNMV | Floating-point maximum number recursive reduction to scalar |
| FMAXP | Floating-point maximum pairwise |
| FMAXP (scalar) | Floating-point maximum of pair of elements (scalar) |
| FMAXP (vector) | Floating-point maximum pairwise (vector) |
| FMAXQV | Floating-point maximum reduction of quadword vector segments |
| FMAXV | Floating-point maximum recursive reduction to scalar |
| FMAXV | Floating-point maximum across vector |
| FMIN (immediate) | Floating-point minimum with immediate (predicated) |
| FMIN (multiple and single vector) | Multi-vector floating-point minimum by vector |
| FMIN (multiple vectors) | Multi-vector floating-point minimum |
| FMIN (scalar) | Floating-point minimum (scalar) |
| FMIN (vector) | Floating-point minimum (vector) |
| FMIN (vectors) | Floating-point minimum (predicated) |
| FMINNM (immediate) | Floating-point minimum number with immediate (predicated) |
| FMINNM (multiple and single vector) | Multi-vector floating-point minimum number by vector |
| FMINNM (multiple vectors) | Multi-vector floating-point minimum number |
| FMINNM (scalar) | Floating-point minimum number (scalar) |
| FMINNM (vector) | Floating-point minimum number (vector) |
| FMINNM (vectors) | Floating-point minimum number (predicated) |
| FMINNMP | Floating-point minimum number pairwise |
| FMINNMP (scalar) | Floating-point minimum number of pair of elements (scalar) |
| FMINNMP (vector) | Floating-point minimum number pairwise (vector) |
| FMINNMQV | Floating-point minimum number recursive reduction of quadword vector segments |
| FMINNMV | Floating-point minimum number recursive reduction to scalar |
| FMINNMV | Floating-point minimum number across vector |
| FMINP | Floating-point minimum pairwise |
| FMINP (scalar) | Floating-point minimum of pair of elements (scalar) |
| FMINP (vector) | Floating-point minimum pairwise (vector) |
| FMINQV | Floating-point minimum recursive reduction of quadword vector segments |
| FMINV | Floating-point minimum across vector |
| FMINV | Floating-point minimum recursive reduction to scalar |
| FMLA (by element) | Floating-point fused multiply-add to accumulator (by element) |
| FMLA (indexed) | Floating-point fused multiply-add by indexed elements (Zda = Zda + Zn * Zm[indexed]) |
| FMLA (multiple and indexed vector) | Multi-vector floating-point fused multiply-add by indexed element |
| FMLA (multiple and single vector) | Multi-vector floating-point fused multiply-add by vector |
| FMLA (multiple vectors) | Multi-vector floating-point fused multiply-add |
| FMLA (vector) | Floating-point fused multiply-add to accumulator (vector) |
| FMLA (vectors) | Floating-point fused multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm] |
| FMLAL (multiple and indexed vector, FP16 to FP32) | Multi-vector floating-point multiply-add long by indexed element |
| FMLAL (multiple and indexed vector, FP8 to FP16) | Multi-vector 8-bit floating-point multiply-add long by indexed element to half-precision |
| FMLAL (multiple and single vector, FP16 to FP32) | Multi-vector floating-point multiply-add long by vector |
| FMLAL (multiple and single vector, FP8 to FP16) | Multi-vector 8-bit floating-point multiply-add long by vector to half-precision |
| FMLAL (multiple vectors, FP16 to FP32) | Multi-vector floating-point multiply-add long |
| FMLAL (multiple vectors, FP8 to FP16) | Multi-vector 8-bit floating-point multiply-add long to half-precision |
| FMLAL, FMLAL2 (by element) | Floating-point fused multiply-add long to accumulator (by element) |
| FMLAL, FMLAL2 (vector) | Floating-point fused multiply-add long to accumulator (vector) |
| FMLALB (indexed, FP16 to FP32) | Half-precision multiply-add long to single-precision (bottom, indexed) |
| FMLALB (indexed, FP8 to FP16) | 8-bit floating-point multiply-add long to half-precision (bottom, indexed) |
| FMLALB (vectors, FP16 to FP32) | Half-precision multiply-add long to single-precision (bottom) |
| FMLALB (vectors, FP8 to FP16) | 8-bit floating-point multiply-add long to half-precision (bottom) |
| FMLALB, FMLALT (by element) | 8-bit floating-point multiply-add long to half-precision (vector, by element) |
| FMLALB, FMLALT (vector) | 8-bit floating-point multiply-add long to half-precision (vector) |
| FMLALL (multiple and indexed vector) | Multi-vector 8-bit floating-point multiply-add long-long by indexed element to single-precision |
| FMLALL (multiple and single vector) | Multi-vector 8-bit floating-point multiply-add long-long by vector to single-precision |
| FMLALL (multiple vectors) | Multi-vector 8-bit floating-point multiply-add long-long to single-precision |
| FMLALLBB (indexed) | 8-bit floating-point multiply-add long long to single-precision (bottom bottom, indexed) |
| FMLALLBB (vectors) | 8-bit floating-point multiply-add long long to single-precision (bottom bottom) |
| FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) | 8-bit floating-point multiply-add long-long to single-precision (vector, by element) |
| FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) | 8-bit floating-point multiply-add long-long to single-precision (vector) |
| FMLALLBT (indexed) | 8-bit floating-point multiply-add long long to single-precision (bottom top, indexed) |
| FMLALLBT (vectors) | 8-bit floating-point multiply-add long long to single-precision (bottom top) |
| FMLALLTB (indexed) | 8-bit floating-point multiply-add long long to single-precision (top bottom, indexed) |
| FMLALLTB (vectors) | 8-bit floating-point multiply-add long long to single-precision (top bottom) |
| FMLALLTT (indexed) | 8-bit floating-point multiply-add long long to single-precision (top top, indexed) |
| FMLALLTT (vectors) | 8-bit floating-point multiply-add long long to single-precision (top top) |
| FMLALT (indexed, FP16 to FP32) | Half-precision multiply-add long to single-precision (top, indexed) |
| FMLALT (indexed, FP8 to FP16) | 8-bit floating-point multiply-add long to half-precision (top, indexed) |
| FMLALT (vectors, FP16 to FP32) | Half-precision multiply-add long to single-precision (top) |
| FMLALT (vectors, FP8 to FP16) | 8-bit floating-point multiply-add long to half-precision (top) |
| FMLS (by element) | Floating-point fused multiply-subtract from accumulator (by element) |
| FMLS (indexed) | Floating-point fused multiply-subtract by indexed elements (Zda = Zda + -Zn * Zm[indexed]) |
| FMLS (multiple and indexed vector) | Multi-vector floating-point fused multiply-subtract by indexed element |
| FMLS (multiple and single vector) | Multi-vector floating-point fused multiply-subtract by vector |
| FMLS (multiple vectors) | Multi-vector floating-point fused multiply-subtract |
| FMLS (vector) | Floating-point fused multiply-subtract from accumulator (vector) |
| FMLS (vectors) | Floating-point fused multiply-subtract vectors (predicated), writing addend [Zda = Zda + -Zn * Zm] |
| FMLSL (multiple and indexed vector) | Multi-vector floating-point multiply-subtract long by indexed element |
| FMLSL (multiple and single vector) | Multi-vector floating-point multiply-subtract long by vector |
| FMLSL (multiple vectors) | Multi-vector floating-point multiply-subtract long |
| FMLSL, FMLSL2 (by element) | Floating-point fused multiply-subtract long from accumulator (by element) |
| FMLSL, FMLSL2 (vector) | Floating-point fused multiply-subtract long from accumulator (vector) |
| FMLSLB (indexed) | Half-precision multiply-subtract long from single-precision (bottom, indexed) |
| FMLSLB (vectors) | Half-precision multiply-subtract long from single-precision (bottom) |
| FMLSLT (indexed) | Half-precision multiply-subtract long from single-precision (top, indexed) |
| FMLSLT (vectors) | Half-precision multiply-subtract long from single-precision (top) |
| FMMLA (non-widening) | Floating-point matrix multiply-accumulate |
| FMMLA (widening, 8-bit floating-point to half-precision) | 8-bit floating-point matrix multiply-accumulate to half-precision |
| FMMLA (widening, 8-bit floating-point to single-precision) | 8-bit floating-point matrix multiply-accumulate to single-precision |
| FMMLA (widening, FP16 to FP32) | Half-precision matrix multiply-accumulate to single-precision |
| FMMLA (widening, FP8 to FP16) | 8-bit floating-point matrix multiply-accumulate to half-precision |
| FMMLA (widening, FP8 to FP32) | 8-bit floating-point matrix multiply-accumulate to single-precision |
| FMOP4A (non-widening) | Floating-point quarter-tile outer products, accumulating |
| FMOP4A (widening, 2-way, FP16 to FP32) | Half-precision quarter-tile sums of two outer products, accumulating |
| FMOP4A (widening, 2-way, FP8 to FP16) | 8-bit floating-point quarter-tile sums of two outer products, accumulating |
| FMOP4A (widening, 4-way) | 8-bit floating-point quarter-tile sums of four outer products, accumulating |
| FMOP4S (non-widening) | Floating-point quarter-tile outer products, subtracting |
| FMOP4S (widening) | Half-precision quarter-tile sums of two outer products, subtracting |
| FMOPA (non-widening) | Floating-point outer product and accumulate |
| FMOPA (widening, 2-way, FP16 to FP32) | Half-precision sum of outer products and accumulate |
| FMOPA (widening, 2-way, FP8 to FP16) | 8-bit floating-point sum of outer products and accumulate |
| FMOPA (widening, 4-way) | 8-bit floating-point sum of outer products and accumulate |
| FMOPS (non-widening) | Floating-point outer product and subtract |
| FMOPS (widening) | Half-precision sum of outer products and subtract |
| FMOV (general) | Floating-point move to or from general-purpose register without conversion |
| FMOV (immediate, predicated) | Move 8-bit floating-point immediate to vector elements (predicated) |
| FMOV (immediate, unpredicated) | Move 8-bit floating-point immediate to vector elements (unpredicated) |
| FMOV (register) | Floating-point move register without conversion |
| FMOV (scalar, immediate) | Floating-point move immediate (scalar) |
| FMOV (vector, immediate) | Floating-point move immediate (vector) |
| FMOV (zero, predicated) | Move floating-point +0.0 to vector elements (predicated) |
| FMOV (zero, unpredicated) | Move floating-point +0.0 to vector elements (unpredicated) |
| FMSB | Floating-point fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za + -Zdn * Zm] |
| FMSUB | Floating-point fused multiply-subtract (scalar) |
| FMUL (by element) | Floating-point multiply (by element) |
| FMUL (immediate) | Floating-point multiply by immediate (predicated) |
| FMUL (indexed) | Floating-point multiply by indexed elements |
| FMUL (multiple and single vector) | Multi-vector floating-point multiply by vector |
| FMUL (multiple vectors) | Multi-vector floating-point multiply |
| FMUL (scalar) | Floating-point multiply (scalar) |
| FMUL (vector) | Floating-point multiply (vector) |
| FMUL (vectors, predicated) | Floating-point multiply vectors (predicated) |
| FMUL (vectors, unpredicated) | Floating-point multiply vectors (unpredicated) |
| FMULX | Floating-point multiply-extended vectors (predicated) |
| FMULX | Floating-point multiply extended |
| FMULX (by element) | Floating-point multiply extended (by element) |
| FNEG | Floating-point negate (predicated) |
| FNEG (scalar) | Floating-point negate (scalar) |
| FNEG (vector) | Floating-point negate (vector) |
| FNMAD | Floating-point negated fused multiply-add vectors (predicated), writing multiplicand [Zdn = -Za + -Zdn * Zm] |
| FNMADD | Floating-point negated fused multiply-add (scalar) |
| FNMLA | Floating-point negated fused multiply-add vectors (predicated), writing addend [Zda = -Zda + -Zn * Zm] |
| FNMLS | Floating-point negated fused multiply-subtract vectors (predicated), writing addend [Zda = -Zda + Zn * Zm] |
| FNMSB | Floating-point negated fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = -Za + Zdn * Zm] |
| FNMSUB | Floating-point negated fused multiply-subtract (scalar) |
| FNMUL (scalar) | Floating-point multiply-negate (scalar) |
| FRECPE | Floating-point reciprocal estimate (unpredicated) |
| FRECPE | Floating-point reciprocal estimate |
| FRECPS | Floating-point reciprocal step (unpredicated) |
| FRECPS | Floating-point reciprocal step |
| FRECPX | Floating-point reciprocal exponent (scalar) |
| FRECPX | Floating-point reciprocal exponent (predicated) |
| FRINT32X | Floating-point round to 32-bit integer, using current rounding mode (predicated) |
| FRINT32X (scalar) | Floating-point round to 32-bit integer, using current rounding mode (scalar) |
| FRINT32X (vector) | Floating-point round to 32-bit integer, using current rounding mode (vector) |
| FRINT32Z | Floating-point round to 32-bit integer, toward zero (predicated) |
| FRINT32Z (scalar) | Floating-point round to 32-bit integer toward zero (scalar) |
| FRINT32Z (vector) | Floating-point round to 32-bit integer toward zero (vector) |
| FRINT64X | Floating-point round to 64-bit integer, using current rounding mode (predicated) |
| FRINT64X (scalar) | Floating-point round to 64-bit integer, using current rounding mode (scalar) |
| FRINT64X (vector) | Floating-point round to 64-bit integer, using current rounding mode (vector) |
| FRINT64Z | Floating-point round to 64-bit integer, toward zero (predicated) |
| FRINT64Z (scalar) | Floating-point round to 64-bit integer toward zero (scalar) |
| FRINT64Z (vector) | Floating-point round to 64-bit integer toward zero (vector) |
| FRINT | Floating-point round to integral value (predicated) |
| FRINTA | Multi-vector floating-point round to integral value, to nearest with ties away from zero |
| FRINTA (scalar) | Floating-point round to integral, to nearest with ties to away (scalar) |
| FRINTA (vector) | Floating-point round to integral, to nearest with ties to away (vector) |
| FRINTI (scalar) | Floating-point round to integral, using current rounding mode (scalar) |
| FRINTI (vector) | Floating-point round to integral, using current rounding mode (vector) |
| FRINTM | Multi-vector floating-point round to integral value, toward minus Infinity |
| FRINTM (scalar) | Floating-point round to integral, toward minus infinity (scalar) |
| FRINTM (vector) | Floating-point round to integral, toward minus infinity (vector) |
| FRINTN | Multi-vector floating-point round to integral value, to nearest with ties to even |
| FRINTN (scalar) | Floating-point round to integral, to nearest with ties to even (scalar) |
| FRINTN (vector) | Floating-point round to integral, to nearest with ties to even (vector) |
| FRINTP | Multi-vector floating-point round to integral value, toward plus Infinity |
| FRINTP (scalar) | Floating-point round to integral, toward plus infinity (scalar) |
| FRINTP (vector) | Floating-point round to integral, toward plus infinity (vector) |
| FRINTX (scalar) | Floating-point round to integral exact, using current rounding mode (scalar) |
| FRINTX (vector) | Floating-point round to integral exact, using current rounding mode (vector) |
| FRINTZ (scalar) | Floating-point round to integral, toward zero (scalar) |
| FRINTZ (vector) | Floating-point round to integral, toward zero (vector) |
| FRSQRTE | Floating-point reciprocal square root estimate |
| FRSQRTE | Floating-point reciprocal square root estimate (unpredicated) |
| FRSQRTS | Floating-point reciprocal square root step |
| FRSQRTS | Floating-point reciprocal square root step (unpredicated) |
| FSCALE | Floating-point adjust exponent by vector (predicated) |
| FSCALE | Floating-point adjust exponent by vector |
| FSCALE (multiple and single vector) | Multi-vector floating-point adjust exponent by vector |
| FSCALE (multiple vectors) | Multi-vector floating-point adjust exponent |
| FSQRT | Floating-point square root (predicated) |
| FSQRT (scalar) | Floating-point square root (scalar) |
| FSQRT (vector) | Floating-point square root (vector) |
| FSUB | Floating-point subtract multi-vector from ZA array vector accumulators |
| FSUB (immediate) | Floating-point subtract immediate (predicated) |
| FSUB (scalar) | Floating-point subtract (scalar) |
| FSUB (vector) | Floating-point subtract (vector) |
| FSUB (vectors, predicated) | Floating-point subtract vectors (predicated) |
| FSUB (vectors, unpredicated) | Floating-point subtract vectors (unpredicated) |
| FSUBR (immediate) | Floating-point reversed subtract from immediate (predicated) |
| FSUBR (vectors) | Floating-point reversed subtract vectors (predicated) |
| FTMAD | Floating-point trigonometric multiply-add coefficient |
| FTMOPA (non-widening) | Floating-point sparse outer product, accumulating |
| FTMOPA (widening, 2-way, FP16 to FP32) | Half-precision sparse sum of two outer products, accumulating |
| FTMOPA (widening, 2-way, FP8 to FP16) | 8-bit floating-point sparse sum of two outer products, accumulating |
| FTMOPA (widening, 4-way) | 8-bit floating-point sparse sum of four outer products, accumulating |
| FTSMUL | Floating-point trigonometric starting value |
| FTSSEL | Floating-point trigonometric select coefficient |
| FVDOT (FP16 to FP32) | Multi-vector half-precision vertical dot-product by indexed element |
| FVDOT (FP8 to FP16) | Multi-vector 8-bit floating-point vertical dot-product by indexed element to half-precision |
| FVDOTB | Multi-vector 8-bit floating-point vertical dot-product by indexed element to single-precision (bottom) |
| FVDOTT | Multi-vector 8-bit floating-point vertical dot-product by indexed element to single-precision (top) |
| GCSB | Guarded Control Stack barrier |
| GCSPOPCX | Guarded Control Stack pop and compare exception return record |
| GCSPOPM | Guarded Control Stack pop |
| GCSPOPX | Guarded Control Stack pop exception return record |
| GCSPUSHM | Guarded Control Stack push |
| GCSPUSHX | Guarded Control Stack push exception return record |
| GCSSS1 | Guarded Control Stack switch stack 1 |
| GCSSS2 | Guarded Control Stack switch stack 2 |
| GCSSTR | Guarded Control Stack store register |
| GCSSTTR | Guarded Control Stack store register (unprivileged) |
| GMI | Tag mask insert |
| HINT | Hint instruction |
| HISTCNT | Count matching elements in vector |
| HISTSEG | Count matching elements in vector segments |
| HLT | Halt instruction |
| HVC | Hypervisor call |
| IC | Instruction cache operation |
| INCB, INCD, INCH, INCW (scalar) | Increment scalar by multiple of predicate constraint element count |
| INCD, INCH, INCW (vector) | Increment vector by multiple of predicate constraint element count |
| INCP (scalar) | Increment scalar by count of true predicate elements |
| INCP (vector) | Increment vector by count of true predicate elements |
| INDEX (immediate, scalar) | Create index starting from immediate and incremented by general-purpose register |
| INDEX (immediates) | Create index starting from and incremented by immediate |
| INDEX (scalar, immediate) | Create index starting from general-purpose register and incremented by immediate |
| INDEX (scalars) | Create index starting from and incremented by general-purpose register |
| INS (element) | Insert vector element from another vector element |
| INS (general) | Insert vector element from general-purpose register |
| INSR (scalar) | Insert general-purpose register in shifted vector |
| INSR (SIMD&FP scalar) | Insert SIMD&FP scalar register in shifted vector |
| IRG | Insert random tag |
| ISB | Instruction synchronization barrier |
| LASTA (scalar) | Extract element after last to general-purpose register |
| LASTA (SIMD&FP scalar) | Extract element after last to SIMD&FP scalar register |
| LASTB (scalar) | Extract last element to general-purpose register |
| LASTB (SIMD&FP scalar) | Extract last element to SIMD&FP scalar register |
| LASTP | Scalar index of last true predicate element (predicated) |
| LD1 (multiple structures) | Load multiple single-element structures to one, two, three, or four registers |
| LD1 (single structure) | Load one single-element structure to one lane of one register |
| LD1B (scalar plus immediate, consecutive registers) | Contiguous load of bytes to multiple consecutive vectors (immediate index) |
| LD1B (scalar plus immediate, single register) | Contiguous load unsigned bytes to vector (immediate index) |
| LD1B (scalar plus immediate, strided registers) | Contiguous load of bytes to multiple strided vectors (immediate index) |
| LD1B (scalar plus scalar, consecutive registers) | Contiguous load of bytes to multiple consecutive vectors (scalar index) |
| LD1B (scalar plus scalar, single register) | Contiguous load unsigned bytes to vector (scalar index) |
| LD1B (scalar plus scalar, strided registers) | Contiguous load of bytes to multiple strided vectors (scalar index) |
| LD1B (scalar plus scalar, tile slice) | Contiguous load of bytes to 8-bit element ZA tile slice |
| LD1B (scalar plus vector) | Gather load unsigned bytes to vector (vector index) |
| LD1B (vector plus immediate) | Gather load unsigned bytes to vector (immediate index) |
| LD1D (scalar plus immediate, consecutive registers) | Contiguous load of doublewords to multiple consecutive vectors (immediate index) |
| LD1D (scalar plus immediate, single register) | Contiguous load unsigned doublewords to vector (immediate index) |
| LD1D (scalar plus immediate, strided registers) | Contiguous load of doublewords to multiple strided vectors (immediate index) |
| LD1D (scalar plus scalar, consecutive registers) | Contiguous load of doublewords to multiple consecutive vectors (scalar index) |
| LD1D (scalar plus scalar, single register) | Contiguous load unsigned doublewords to vector (scalar index) |
| LD1D (scalar plus scalar, strided registers) | Contiguous load of doublewords to multiple strided vectors (scalar index) |
| LD1D (scalar plus scalar, tile slice) | Contiguous load of doublewords to 64-bit element ZA tile slice |
| LD1D (scalar plus vector) | Gather load doublewords to vector (vector index) |
| LD1D (vector plus immediate) | Gather load doublewords to vector (immediate index) |
| LD1H (scalar plus immediate, consecutive registers) | Contiguous load of halfwords to multiple consecutive vectors (immediate index) |
| LD1H (scalar plus immediate, single register) | Contiguous load unsigned halfwords to vector (immediate index) |
| LD1H (scalar plus immediate, strided registers) | Contiguous load of halfwords to multiple strided vectors (immediate index) |
| LD1H (scalar plus scalar, consecutive registers) | Contiguous load of halfwords to multiple consecutive vectors (scalar index) |
| LD1H (scalar plus scalar, single register) | Contiguous load unsigned halfwords to vector (scalar index) |
| LD1H (scalar plus scalar, strided registers) | Contiguous load of halfwords to multiple strided vectors (scalar index) |
| LD1H (scalar plus scalar, tile slice) | Contiguous load of halfwords to 16-bit element ZA tile slice |
| LD1H (scalar plus vector) | Gather load unsigned halfwords to vector (vector index) |
| LD1H (vector plus immediate) | Gather load unsigned halfwords to vector (immediate index) |
| LD1Q | Contiguous load of quadwords to 128-bit element ZA tile slice |
| LD1Q | Gather load quadwords |
| LD1R | Load one single-element structure and replicate to all lanes (of one register) |
| LD1RB | Load and broadcast unsigned byte to vector |
| LD1RD | Load and broadcast doubleword to vector |
| LD1RH | Load and broadcast unsigned halfword to vector |
| LD1ROB (scalar plus immediate) | Contiguous load and replicate thirty-two bytes (immediate index) |
| LD1ROB (scalar plus scalar) | Contiguous load and replicate thirty-two bytes (scalar index) |
| LD1ROD (scalar plus immediate) | Contiguous load and replicate four doublewords (immediate index) |
| LD1ROD (scalar plus scalar) | Contiguous load and replicate four doublewords (scalar index) |
| LD1ROH (scalar plus immediate) | Contiguous load and replicate sixteen halfwords (immediate index) |
| LD1ROH (scalar plus scalar) | Contiguous load and replicate sixteen halfwords (scalar index) |
| LD1ROW (scalar plus immediate) | Contiguous load and replicate eight words (immediate index) |
| LD1ROW (scalar plus scalar) | Contiguous load and replicate eight words (scalar index) |
| LD1RQB (scalar plus immediate) | Contiguous load and replicate sixteen bytes (immediate index) |
| LD1RQB (scalar plus scalar) | Contiguous load and replicate sixteen bytes (scalar index) |
| LD1RQD (scalar plus immediate) | Contiguous load and replicate two doublewords (immediate index) |
| LD1RQD (scalar plus scalar) | Contiguous load and replicate two doublewords (scalar index) |
| LD1RQH (scalar plus immediate) | Contiguous load and replicate eight halfwords (immediate index) |
| LD1RQH (scalar plus scalar) | Contiguous load and replicate eight halfwords (scalar index) |
| LD1RQW (scalar plus immediate) | Contiguous load and replicate four words (immediate index) |
| LD1RQW (scalar plus scalar) | Contiguous load and replicate four words (scalar index) |
| LD1RSB | Load and broadcast signed byte to vector |
| LD1RSH | Load and broadcast signed halfword to vector |
| LD1RSW | Load and broadcast signed word to vector |
| LD1RW | Load and broadcast unsigned word to vector |
| LD1SB (scalar plus immediate) | Contiguous load signed bytes to vector (immediate index) |
| LD1SB (scalar plus scalar) | Contiguous load signed bytes to vector (scalar index) |
| LD1SB (scalar plus vector) | Gather load signed bytes to vector (vector index) |
| LD1SB (vector plus immediate) | Gather load signed bytes to vector (immediate index) |
| LD1SH (scalar plus immediate) | Contiguous load signed halfwords to vector (immediate index) |
| LD1SH (scalar plus scalar) | Contiguous load signed halfwords to vector (scalar index) |
| LD1SH (scalar plus vector) | Gather load signed halfwords to vector (vector index) |
| LD1SH (vector plus immediate) | Gather load signed halfwords to vector (immediate index) |
| LD1SW (scalar plus immediate) | Contiguous load signed words to vector (immediate index) |
| LD1SW (scalar plus scalar) | Contiguous load signed words to vector (scalar index) |
| LD1SW (scalar plus vector) | Gather load signed words to vector (vector index) |
| LD1SW (vector plus immediate) | Gather load signed words to vector (immediate index) |
| LD1W (scalar plus immediate, consecutive registers) | Contiguous load of words to multiple consecutive vectors (immediate index) |
| LD1W (scalar plus immediate, single register) | Contiguous load unsigned words to vector (immediate index) |
| LD1W (scalar plus immediate, strided registers) | Contiguous load of words to multiple strided vectors (immediate index) |
| LD1W (scalar plus scalar, consecutive registers) | Contiguous load of words to multiple consecutive vectors (scalar index) |
| LD1W (scalar plus scalar, single register) | Contiguous load unsigned words to vector (scalar index) |
| LD1W (scalar plus scalar, strided registers) | Contiguous load of words to multiple strided vectors (scalar index) |
| LD1W (scalar plus scalar, tile slice) | Contiguous load of words to 32-bit element ZA tile slice |
| LD1W (scalar plus vector) | Gather load unsigned words to vector (vector index) |
| LD1W (vector plus immediate) | Gather load unsigned words to vector (immediate index) |
| LD2 (multiple structures) | Load multiple 2-element structures to two registers |
| LD2 (single structure) | Load single 2-element structure to one lane of two registers |
| LD2B (scalar plus immediate) | Contiguous load two-byte structures to two vectors (immediate index) |
| LD2B (scalar plus scalar) | Contiguous load two-byte structures to two vectors (scalar index) |
| LD2D (scalar plus immediate) | Contiguous load two-doubleword structures to two vectors (immediate index) |
| LD2D (scalar plus scalar) | Contiguous load two-doubleword structures to two vectors (scalar index) |
| LD2H (scalar plus immediate) | Contiguous load two-halfword structures to two vectors (immediate index) |
| LD2H (scalar plus scalar) | Contiguous load two-halfword structures to two vectors (scalar index) |
| LD2Q (scalar plus immediate) | Contiguous load two-quadword structures to two vectors (immediate index) |
| LD2Q (scalar plus scalar) | Contiguous load two-quadword structures to two vectors (scalar index) |
| LD2R | Load single 2-element structure and replicate to all lanes of two registers |
| LD2W (scalar plus immediate) | Contiguous load two-word structures to two vectors (immediate index) |
| LD2W (scalar plus scalar) | Contiguous load two-word structures to two vectors (scalar index) |
| LD3 (multiple structures) | Load multiple 3-element structures to three registers |
| LD3 (single structure) | Load single 3-element structure to one lane of three registers |
| LD3B (scalar plus immediate) | Contiguous load three-byte structures to three vectors (immediate index) |
| LD3B (scalar plus scalar) | Contiguous load three-byte structures to three vectors (scalar index) |
| LD3D (scalar plus immediate) | Contiguous load three-doubleword structures to three vectors (immediate index) |
| LD3D (scalar plus scalar) | Contiguous load three-doubleword structures to three vectors (scalar index) |
| LD3H (scalar plus immediate) | Contiguous load three-halfword structures to three vectors (immediate index) |
| LD3H (scalar plus scalar) | Contiguous load three-halfword structures to three vectors (scalar index) |
| LD3Q (scalar plus immediate) | Contiguous load three-quadword structures to three vectors (immediate index) |
| LD3Q (scalar plus scalar) | Contiguous load three-quadword structures to three vectors (scalar index) |
| LD3R | Load single 3-element structure and replicate to all lanes of three registers |
| LD3W (scalar plus immediate) | Contiguous load three-word structures to three vectors (immediate index) |
| LD3W (scalar plus scalar) | Contiguous load three-word structures to three vectors (scalar index) |
| LD4 (multiple structures) | Load multiple 4-element structures to four registers |
| LD4 (single structure) | Load single 4-element structure to one lane of four registers |
| LD4B (scalar plus immediate) | Contiguous load four-byte structures to four vectors (immediate index) |
| LD4B (scalar plus scalar) | Contiguous load four-byte structures to four vectors (scalar index) |
| LD4D (scalar plus immediate) | Contiguous load four-doubleword structures to four vectors (immediate index) |
| LD4D (scalar plus scalar) | Contiguous load four-doubleword structures to four vectors (scalar index) |
| LD4H (scalar plus immediate) | Contiguous load four-halfword structures to four vectors (immediate index) |
| LD4H (scalar plus scalar) | Contiguous load four-halfword structures to four vectors (scalar index) |
| LD4Q (scalar plus immediate) | Contiguous load four-quadword structures to four vectors (immediate index) |
| LD4Q (scalar plus scalar) | Contiguous load four-quadword structures to four vectors (scalar index) |
| LD4R | Load single 4-element structure and replicate to all lanes of four registers |
| LD4W (scalar plus immediate) | Contiguous load four-word structures to four vectors (immediate index) |
| LD4W (scalar plus scalar) | Contiguous load four-word structures to four vectors (scalar index) |
| LD64B | Single-copy atomic 64-byte Load |
| LDADD, LDADDA, LDADDAL, LDADDL | Atomic add on word or doubleword in memory |
| LDADDB, LDADDAB, LDADDALB, LDADDLB | Atomic add on byte in memory |
| LDADDH, LDADDAH, LDADDALH, LDADDLH | Atomic add on halfword in memory |
| LDAP1 (SIMD&FP) | Load-acquire RCpc one single-element structure to one lane of one register |
| LDAPR | Load-acquire RCpc register |
| LDAPRB | Load-acquire RCpc register byte |
| LDAPRH | Load-acquire RCpc register halfword |
| LDAPUR | Load-acquire RCpc register (unscaled) |
| LDAPUR (SIMD&FP) | Load-acquire RCpc SIMD&FP register (unscaled offset) |
| LDAPURB | Load-acquire RCpc register byte (unscaled) |
| LDAPURH | Load-acquire RCpc register halfword (unscaled) |
| LDAPURSB | Load-acquire RCpc register signed byte (unscaled) |
| LDAPURSH | Load-acquire RCpc register signed halfword (unscaled) |
| LDAPURSW | Load-acquire RCpc register signed word (unscaled) |
| LDAR | Load-acquire register |
| LDARB | Load-acquire register byte |
| LDARH | Load-acquire register halfword |
| LDATXR | Load-acquire unprivileged exclusive register |
| LDAXP | Load-acquire exclusive pair of registers |
| LDAXR | Load-acquire exclusive register |
| LDAXRB | Load-acquire exclusive register byte |
| LDAXRH | Load-acquire exclusive register halfword |
| LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL | BFloat16 floating-point add in memory |
| LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL | BFloat16 floating-point atomic maximum in memory |
| LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML | BFloat16 floating-point atomic maximum number in memory |
| LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL | BFloat16 floating-point atomic minimum in memory |
| LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML | BFloat16 floating-point atomic minimum number in memory |
| LDCLR, LDCLRA, LDCLRAL, LDCLRL | Atomic bit clear on word or doubleword in memory |
| LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB | Atomic bit clear on byte in memory |
| LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH | Atomic bit clear on halfword in memory |
| LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL | Atomic bit clear on quadword in memory |
| LDEOR, LDEORA, LDEORAL, LDEORL | Atomic exclusive-OR on word or doubleword in memory |
| LDEORB, LDEORAB, LDEORALB, LDEORLB | Atomic exclusive-OR on byte in memory |
| LDEORH, LDEORAH, LDEORALH, LDEORLH | Atomic exclusive-OR on halfword in memory |
| LDFADD, LDFADDA, LDFADDAL, LDFADDL | Floating-point atomic add in memory |
| LDFF1B (scalar plus scalar) | Contiguous load first-fault unsigned bytes to vector (scalar index) |
| LDFF1B (scalar plus vector) | Gather load first-fault unsigned bytes to vector (vector index) |
| LDFF1B (vector plus immediate) | Gather load first-fault unsigned bytes to vector (immediate index) |
| LDFF1D (scalar plus scalar) | Contiguous load first-fault doublewords to vector (scalar index) |
| LDFF1D (scalar plus vector) | Gather load first-fault doublewords to vector (vector index) |
| LDFF1D (vector plus immediate) | Gather load first-fault doublewords to vector (immediate index) |
| LDFF1H (scalar plus scalar) | Contiguous load first-fault unsigned halfwords to vector (scalar index) |
| LDFF1H (scalar plus vector) | Gather load first-fault unsigned halfwords to vector (vector index) |
| LDFF1H (vector plus immediate) | Gather load first-fault unsigned halfwords to vector (immediate index) |
| LDFF1SB (scalar plus scalar) | Contiguous load first-fault signed bytes to vector (scalar index) |
| LDFF1SB (scalar plus vector) | Gather load first-fault signed bytes to vector (vector index) |
| LDFF1SB (vector plus immediate) | Gather load first-fault signed bytes to vector (immediate index) |
| LDFF1SH (scalar plus scalar) | Contiguous load first-fault signed halfwords to vector (scalar index) |
| LDFF1SH (scalar plus vector) | Gather load first-fault signed halfwords to vector (vector index) |
| LDFF1SH (vector plus immediate) | Gather load first-fault signed halfwords to vector (immediate index) |
| LDFF1SW (scalar plus scalar) | Contiguous load first-fault signed words to vector (scalar index) |
| LDFF1SW (scalar plus vector) | Gather load first-fault signed words to vector (vector index) |
| LDFF1SW (vector plus immediate) | Gather load first-fault signed words to vector (immediate index) |
| LDFF1W (scalar plus scalar) | Contiguous load first-fault unsigned words to vector (scalar index) |
| LDFF1W (scalar plus vector) | Gather load first-fault unsigned words to vector (vector index) |
| LDFF1W (vector plus immediate) | Gather load first-fault unsigned words to vector (immediate index) |
| LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL | Floating-point atomic maximum in memory |
| LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML | Floating-point atomic maximum number in memory |
| LDFMIN, LDFMINA, LDFMINAL, LDFMINL | Floating-point atomic minimum in memory |
| LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML | Floating-point atomic minimum number in memory |
| LDG | Load Allocation Tag |
| LDGM | Load tag multiple |
| LDIAPP | Load-Acquire RCpc ordered pair of registers |
| LDLAR | Load LOAcquire register |
| LDLARB | Load LOAcquire register byte |
| LDLARH | Load LOAcquire register halfword |
| LDNF1B | Contiguous load non-fault unsigned bytes to vector (immediate index) |
| LDNF1D | Contiguous load non-fault doublewords to vector (immediate index) |
| LDNF1H | Contiguous load non-fault unsigned halfwords to vector (immediate index) |
| LDNF1SB | Contiguous load non-fault signed bytes to vector (immediate index) |
| LDNF1SH | Contiguous load non-fault signed halfwords to vector (immediate index) |
| LDNF1SW | Contiguous load non-fault signed words to vector (immediate index) |
| LDNF1W | Contiguous load non-fault unsigned words to vector (immediate index) |
| LDNP | Load pair of registers, with non-temporal hint |
| LDNP (SIMD&FP) | Load pair of SIMD&FP registers, with non-temporal hint |
| LDNT1B (scalar plus immediate, consecutive registers) | Contiguous load non-temporal of bytes to multiple consecutive vectors (immediate index) |
| LDNT1B (scalar plus immediate, single register) | Contiguous load non-temporal bytes to vector (immediate index) |
| LDNT1B (scalar plus immediate, strided registers) | Contiguous load non-temporal of bytes to multiple strided vectors (immediate index) |
| LDNT1B (scalar plus scalar, consecutive registers) | Contiguous load non-temporal of bytes to multiple consecutive vectors (scalar index) |
| LDNT1B (scalar plus scalar, single register) | Contiguous load non-temporal bytes to vector (scalar index) |
| LDNT1B (scalar plus scalar, strided registers) | Contiguous load non-temporal of bytes to multiple strided vectors (scalar index) |
| LDNT1B (vector plus scalar) | Gather load non-temporal unsigned bytes |
| LDNT1D (scalar plus immediate, consecutive registers) | Contiguous load non-temporal of doublewords to multiple consecutive vectors (immediate index) |
| LDNT1D (scalar plus immediate, single register) | Contiguous load non-temporal doublewords to vector (immediate index) |
| LDNT1D (scalar plus immediate, strided registers) | Contiguous load non-temporal of doublewords to multiple strided vectors (immediate index) |
| LDNT1D (scalar plus scalar, consecutive registers) | Contiguous load non-temporal of doublewords to multiple consecutive vectors (scalar index) |
| LDNT1D (scalar plus scalar, single register) | Contiguous load non-temporal doublewords to vector (scalar index) |
| LDNT1D (scalar plus scalar, strided registers) | Contiguous load non-temporal of doublewords to multiple strided vectors (scalar index) |
| LDNT1D (vector plus scalar) | Gather load non-temporal unsigned doublewords |
| LDNT1H (scalar plus immediate, consecutive registers) | Contiguous load non-temporal of halfwords to multiple consecutive vectors (immediate index) |
| LDNT1H (scalar plus immediate, single register) | Contiguous load non-temporal halfwords to vector (immediate index) |
| LDNT1H (scalar plus immediate, strided registers) | Contiguous load non-temporal of halfwords to multiple strided vectors (immediate index) |
| LDNT1H (scalar plus scalar, consecutive registers) | Contiguous load non-temporal of halfwords to multiple consecutive vectors (scalar index) |
| LDNT1H (scalar plus scalar, single register) | Contiguous load non-temporal halfwords to vector (scalar index) |
| LDNT1H (scalar plus scalar, strided registers) | Contiguous load non-temporal of halfwords to multiple strided vectors (scalar index) |
| LDNT1H (vector plus scalar) | Gather load non-temporal unsigned halfwords |
| LDNT1SB | Gather load non-temporal signed bytes |
| LDNT1SH | Gather load non-temporal signed halfwords |
| LDNT1SW | Gather load non-temporal signed words |
| LDNT1W (scalar plus immediate, consecutive registers) | Contiguous load non-temporal of words to multiple consecutive vectors (immediate index) |
| LDNT1W (scalar plus immediate, single register) | Contiguous load non-temporal words to vector (immediate index) |
| LDNT1W (scalar plus immediate, strided registers) | Contiguous load non-temporal of words to multiple strided vectors (immediate index) |
| LDNT1W (scalar plus scalar, consecutive registers) | Contiguous load non-temporal of words to multiple consecutive vectors (scalar index) |
| LDNT1W (scalar plus scalar, single register) | Contiguous load non-temporal words to vector (scalar index) |
| LDNT1W (scalar plus scalar, strided registers) | Contiguous load non-temporal of words to multiple strided vectors (scalar index) |
| LDNT1W (vector plus scalar) | Gather load non-temporal unsigned words |
| LDP | Load pair of registers |
| LDP (SIMD&FP) | Load pair of SIMD&FP registers |
| LDPSW | Load pair of registers signed word |
| LDR (array vector) | Load ZA array vector |
| LDR (immediate) | Load register (immediate) |
| LDR (immediate, SIMD&FP) | Load SIMD&FP register (immediate offset) |
| LDR (literal) | Load register (literal) |
| LDR (literal, SIMD&FP) | Load SIMD&FP register (PC-relative literal) |
| LDR (predicate) | Load predicate register |
| LDR (register) | Load register (register) |
| LDR (register, SIMD&FP) | Load SIMD&FP register (register offset) |
| LDR (table) | Load ZT0 register |
| LDR (vector) | Load vector register |
| LDRAA, LDRAB | Load register, with pointer authentication |
| LDRB (immediate) | Load register byte (immediate) |
| LDRB (register) | Load register byte (register) |
| LDRH (immediate) | Load register halfword (immediate) |
| LDRH (register) | Load register halfword (register) |
| LDRSB (immediate) | Load register signed byte (immediate) |
| LDRSB (register) | Load register signed byte (register) |
| LDRSH (immediate) | Load register signed halfword (immediate) |
| LDRSH (register) | Load register signed halfword (register) |
| LDRSW (immediate) | Load register signed word (immediate) |
| LDRSW (literal) | Load register signed word (literal) |
| LDRSW (register) | Load register signed word (register) |
| LDSET, LDSETA, LDSETAL, LDSETL | Atomic bit set on word or doubleword in memory |
| LDSETB, LDSETAB, LDSETALB, LDSETLB | Atomic bit set on byte in memory |
| LDSETH, LDSETAH, LDSETALH, LDSETLH | Atomic bit set on halfword in memory |
| LDSETP, LDSETPA, LDSETPAL, LDSETPL | Atomic bit set on quadword in memory |
| LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL | Atomic signed maximum on word or doubleword in memory |
| LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB | Atomic signed maximum on byte in memory |
| LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH | Atomic signed maximum on halfword in memory |
| LDSMIN, LDSMINA, LDSMINAL, LDSMINL | Atomic signed minimum on word or doubleword in memory |
| LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB | Atomic signed minimum on byte in memory |
| LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH | Atomic signed minimum on halfword in memory |
| LDTADD, LDTADDA, LDTADDAL, LDTADDL | Atomic add unprivileged |
| LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL | Atomic bit clear unprivileged |
| LDTNP | Load unprivileged pair of registers, with non-temporal hint |
| LDTNP (SIMD&FP) | Load unprivileged pair of SIMD&FP registers, with non-temporal hint |
| LDTP | Load unprivileged pair of registers |
| LDTP (SIMD&FP) | Load unprivileged pair of SIMD&FP registers |
| LDTR | Load register (unprivileged) |
| LDTRB | Load register byte (unprivileged) |
| LDTRH | Load register halfword (unprivileged) |
| LDTRSB | Load register signed byte (unprivileged) |
| LDTRSH | Load register signed halfword (unprivileged) |
| LDTRSW | Load register signed word (unprivileged) |
| LDTSET, LDTSETA, LDTSETAL, LDTSETL | Atomic bit set unprivileged |
| LDTXR | Load unprivileged exclusive register |
| LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL | Atomic unsigned maximum on word or doubleword in memory |
| LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB | Atomic unsigned maximum on byte in memory |
| LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH | Atomic unsigned maximum on halfword in memory |
| LDUMIN, LDUMINA, LDUMINAL, LDUMINL | Atomic unsigned minimum on word or doubleword in memory |
| LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB | Atomic unsigned minimum on byte in memory |
| LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH | Atomic unsigned minimum on halfword in memory |
| LDUR | Load register (unscaled) |
| LDUR (SIMD&FP) | Load SIMD&FP register (unscaled offset) |
| LDURB | Load register byte (unscaled) |
| LDURH | Load register halfword (unscaled) |
| LDURSB | Load register signed byte (unscaled) |
| LDURSH | Load register signed halfword (unscaled) |
| LDURSW | Load register signed word (unscaled) |
| LDXP | Load exclusive pair of registers |
| LDXR | Load exclusive register |
| LDXRB | Load exclusive register byte |
| LDXRH | Load exclusive register halfword |
| LSL (immediate) | Logical shift left (immediate) |
| LSL (immediate, predicated) | Logical shift left by immediate (predicated) |
| LSL (immediate, unpredicated) | Logical shift left by immediate (unpredicated) |
| LSL (register) | Logical shift left (register) |
| LSL (vectors) | Logical shift left by vector (predicated) |
| LSL (wide elements, predicated) | Logical shift left by 64-bit wide elements (predicated) |
| LSL (wide elements, unpredicated) | Logical shift left by 64-bit wide elements (unpredicated) |
| LSLR | Reversed logical shift left by vector (predicated) |
| LSLV | Logical shift left variable |
| LSR (immediate) | Logical shift right (immediate) |
| LSR (immediate, predicated) | Logical shift right by immediate (predicated) |
| LSR (immediate, unpredicated) | Logical shift right by immediate (unpredicated) |
| LSR (register) | Logical shift right (register) |
| LSR (vectors) | Logical shift right by vector (predicated) |
| LSR (wide elements, predicated) | Logical shift right by 64-bit wide elements (predicated) |
| LSR (wide elements, unpredicated) | Logical shift right by 64-bit wide elements (unpredicated) |
| LSRR | Reversed logical shift right by vector (predicated) |
| LSRV | Logical shift right variable |
| LUTI2 | Lookup table read with 2-bit indices |
| LUTI2 (8-bit and 16-bit) | Lookup table read with 2-bit indices (8-bit and 16-bit) |
| LUTI2 (four registers) | Lookup table read with 2-bit indexes (four registers) |
| LUTI2 (single) | Lookup table read with 2-bit indexes (single) |
| LUTI2 (two registers) | Lookup table read with 2-bit indexes (two registers) |
| LUTI4 | Lookup table read with 4-bit indices |
| LUTI4 (8-bit and 16-bit) | Lookup table read with 4-bit indicess (8-bit and 16-bit) |
| LUTI4 (four registers, 16-bit and 32-bit) | Lookup table read with 4-bit indexes (four registers) |
| LUTI4 (four registers, 8-bit) | Lookup table read with 4-bit indexes and 8-bit elements (four registers) |
| LUTI4 (single) | Lookup table read with 4-bit indexes (single) |
| LUTI4 (two registers) | Lookup table read with 4-bit indexes (two registers) |
| MAD | Multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm] |
| MADD | Multiply-add |
| MADDPT | Multiply-add checked pointer |
| MADPT | Multiply-add checked pointer vectors, writing multiplicand [Zdn = Za + Zdn * Zm] |
| MATCH | Detect any matching elements, setting the condition flags |
| MLA (by element) | Multiply-add to accumulator (vector, by element) |
| MLA (indexed) | Multiply-add to accumulator (indexed) |
| MLA (vector) | Multiply-add to accumulator (vector) |
| MLA (vectors) | Multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm] |
| MLAPT | Multiply-add checked pointer vectors, writing addend [Zda = Zda + Zn * Zm] |
| MLS (by element) | Multiply-subtract from accumulator (vector, by element) |
| MLS (indexed) | Multiply-subtract from accumulator (indexed) |
| MLS (vector) | Multiply-subtract from accumulator (vector) |
| MLS (vectors) | Multiply-subtract vectors (predicated), writing addend [Zda = Zda - Zn * Zm] |
| MNEG | Multiply-negate |
| MOV | Move logical bitmask immediate to vector (unpredicated) |
| MOV | Move predicate (unpredicated) |
| MOV (array to vector, four registers) | Move four ZA single-vector groups to four vector registers |
| MOV (array to vector, two registers) | Move two ZA single-vector groups to two vector registers |
| MOV (bitmask immediate) | Move bitmask immediate value |
| MOV (element) | Move vector element to another vector element |
| MOV (from general) | Move general-purpose register to a vector element |
| MOV (immediate, merging) | Move signed integer immediate to vector elements (merging) |
| MOV (immediate, unpredicated) | Move signed immediate to vector elements (unpredicated) |
| MOV (immediate, zeroing) | Move signed integer immediate to vector elements (zeroing) |
| MOV (inverted wide immediate) | Move inverted wide immediate value |
| MOV (predicate, merging) | Move predicates (merging) |
| MOV (predicate, zeroing) | Move predicates (zeroing) |
| MOV (register) | Move register value |
| MOV (scalar) | Move vector element to scalar |
| MOV (scalar, predicated) | Move general-purpose register to vector elements (predicated) |
| MOV (scalar, unpredicated) | Move general-purpose register to vector elements (unpredicated) |
| MOV (SIMD&FP scalar, predicated) | Move SIMD&FP scalar register to vector elements (predicated) |
| MOV (SIMD&FP scalar, unpredicated) | Move indexed element or SIMD&FP scalar to vector (unpredicated) |
| MOV (tile to vector, four registers) | Move four ZA tile slices to four vector registers |
| MOV (tile to vector, single) | Move ZA tile slice to vector register |
| MOV (tile to vector, two registers) | Move two ZA tile slices to two vector registers |
| MOV (to general) | Move vector element to general-purpose register |
| MOV (to/from SP) | Move register value to or from SP |
| MOV (vector to array, four registers) | Move four vector registers to four ZA single-vector groups |
| MOV (vector to array, two registers) | Move two vector registers to two ZA single-vector groups |
| MOV (vector to tile, four registers) | Move four vector registers to four ZA tile slices |
| MOV (vector to tile, single) | Move vector register to ZA tile slice |
| MOV (vector to tile, two registers) | Move two vector registers to two ZA tile slices |
| MOV (vector) | Move vector |
| MOV (vector, predicated) | Move vector elements (predicated) |
| MOV (vector, unpredicated) | Move vector register (unpredicated) |
| MOV (wide immediate) | Move wide immediate value |
| MOVA (array to vector, four registers) | Move four ZA single-vector groups to four vector registers |
| MOVA (array to vector, two registers) | Move two ZA single-vector groups to two vector registers |
| MOVA (tile to vector, four registers) | Move four ZA tile slices to four vector registers |
| MOVA (tile to vector, single) | Move ZA tile slice to vector register |
| MOVA (tile to vector, two registers) | Move two ZA tile slices to two vector registers |
| MOVA (vector to array, four registers) | Move four vector registers to four ZA single-vector groups |
| MOVA (vector to array, two registers) | Move two vector registers to two ZA single-vector groups |
| MOVA (vector to tile, four registers) | Move four vector registers to four ZA tile slices |
| MOVA (vector to tile, single) | Move vector register to ZA tile slice |
| MOVA (vector to tile, two registers) | Move two vector registers to two ZA tile slices |
| MOVAZ (array to vector, four registers) | Move and zero four ZA single-vector groups to vector registers |
| MOVAZ (array to vector, two registers) | Move and zero two ZA single-vector groups to vector registers |
| MOVAZ (tile to vector, four registers) | Move and zero four ZA tile slices to vector registers |
| MOVAZ (tile to vector, single) | Move and zero ZA tile slice to vector register |
| MOVAZ (tile to vector, two registers) | Move and zero two ZA tile slices to vector registers |
| MOVI | Move immediate (vector) |
| MOVK | Move wide with keep |
| MOVN | Move wide with NOT |
| MOVPRFX (predicated) | Move prefix (predicated) |
| MOVPRFX (unpredicated) | Move prefix (unpredicated) |
| MOVS (predicated) | Move predicates (zeroing), setting the condition flags |
| MOVS (unpredicated) | Move predicate (unpredicated), setting the condition flags |
| MOVT (scalar to table) | Move 8 bytes from general-purpose register to ZT0 |
| MOVT (table to scalar) | Move 8 bytes from ZT0 to general-purpose register |
| MOVT (vector to table) | Move vector register to ZT0 |
| MOVZ | Move wide with zero |
| MRRS | Move System register to two adjacent general-purpose registers |
| MRS | Move System register to general-purpose register |
| MSB | Multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za - Zdn * Zm] |
| MSR (immediate) | Move immediate value to special register |
| MSR (register) | Move general-purpose register to System register |
| MSRR | Move two adjacent general-purpose registers to System register |
| MSUB | Multiply-subtract |
| MSUBPT | Multiply-subtract checked pointer |
| MUL | Multiply |
| MUL (by element) | Multiply (vector, by element) |
| MUL (immediate) | Multiply by immediate (unpredicated) |
| MUL (indexed) | Multiply (indexed) |
| MUL (vector) | Multiply (vector) |
| MUL (vectors, predicated) | Multiply vectors (predicated) |
| MUL (vectors, unpredicated) | Multiply vectors (unpredicated) |
| MVN | Bitwise NOT (vector) |
| MVN | Bitwise NOT |
| MVNI | Move inverted immediate (vector) |
| NAND | Bitwise NAND predicates |
| NANDS | Bitwise NAND predicates, setting the condition flags |
| NBSL | Bitwise inverted select |
| NEG | Negate (predicated) |
| NEG (shifted register) | Negate (shifted register) |
| NEG (vector) | Negate (vector) |
| NEGS | Negate, setting flags |
| NGC | Negate with carry |
| NGCS | Negate with carry, setting flags |
| NMATCH | Detect no matching elements, setting the condition flags |
| NOP | No operation |
| NOR | Bitwise NOR predicates |
| NORS | Bitwise NOR predicates, setting the condition flags |
| NOT | Bitwise NOT (vector) |
| NOT (predicate) | Bitwise invert predicate |
| NOT (vector) | Bitwise invert vector (predicated) |
| NOTS | Bitwise invert predicate, setting the condition flags |
| ORN (immediate) | Bitwise inclusive OR with inverted immediate (unpredicated) |
| ORN (predicates) | Bitwise inclusive OR inverted predicate |
| ORN (shifted register) | Bitwise OR NOT (shifted register) |
| ORN (vector) | Bitwise inclusive OR NOT (vector) |
| ORNS | Bitwise inclusive OR inverted predicate, setting the condition flags |
| ORQV | Bitwise inclusive OR reduction of quadword vector segments |
| ORR (immediate) | Bitwise OR (immediate) |
| ORR (immediate) | Bitwise inclusive OR with immediate (unpredicated) |
| ORR (predicates) | Bitwise inclusive OR predicates |
| ORR (shifted register) | Bitwise OR (shifted register) |
| ORR (vector, immediate) | Bitwise inclusive OR (vector, immediate) |
| ORR (vector, register) | Bitwise inclusive OR (vector, register) |
| ORR (vectors, predicated) | Bitwise inclusive OR vectors (predicated) |
| ORR (vectors, unpredicated) | Bitwise inclusive OR vectors (unpredicated) |
| ORRS | Bitwise inclusive OR predicates, setting the condition flags |
| ORV | Bitwise inclusive OR reduction to scalar |
| PACDA, PACDZA | Pointer Authentication Code for data address, using key A |
| PACDB, PACDZB | Pointer Authentication Code for data address, using key B |
| PACGA | Pointer Authentication Code, using generic key |
| PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA | Pointer Authentication Code for instruction address, using key A |
| PACIA171615 | Pointer Authentication Code for instruction address, using key A |
| PACIASPPC | Pointer Authentication Code for return address, using key A |
| PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB | Pointer Authentication Code for instruction address, using key B |
| PACIB171615 | Pointer Authentication Code for instruction address, using key B |
| PACIBSPPC | Pointer Authentication Code for return address, using key B |
| PACM | Pointer authentication modifier |
| PACNBIASPPC | Pointer Authentication Code for return address, using key A, not a branch target |
| PACNBIBSPPC | Pointer Authentication Code for return address, using key B, not a branch target |
| PEXT (predicate pair) | Predicate extract pair from predicate-as-counter |
| PEXT (predicate) | Predicate extract from predicate-as-counter |
| PFALSE | Set all predicate elements to false |
| PFIRST | Set the first active predicate element to true |
| PMLAL | Multi-vector polynomial multiply long and accumulate vectors |
| PMOV (to predicate) | Move predicate from vector |
| PMOV (to vector) | Move predicate to vector |
| PMUL | Polynomial multiply |
| PMUL | Polynomial multiply vectors (unpredicated) |
| PMULL | Multi-vector polynomial multiply long |
| PMULL, PMULL2 | Polynomial multiply long |
| PMULLB | Polynomial multiply long (bottom) |
| PMULLT | Polynomial multiply long (top) |
| PNEXT | Find next active predicate |
| PRFB (scalar plus immediate) | Contiguous prefetch bytes (immediate index) |
| PRFB (scalar plus scalar) | Contiguous prefetch bytes (scalar index) |
| PRFB (scalar plus vector) | Gather prefetch bytes (scalar plus vector) |
| PRFB (vector plus immediate) | Gather prefetch bytes (vector plus immediate) |
| PRFD (scalar plus immediate) | Contiguous prefetch doublewords (immediate index) |
| PRFD (scalar plus scalar) | Contiguous prefetch doublewords (scalar index) |
| PRFD (scalar plus vector) | Gather prefetch doublewords (scalar plus vector) |
| PRFD (vector plus immediate) | Gather prefetch doublewords (vector plus immediate) |
| PRFH (scalar plus immediate) | Contiguous prefetch halfwords (immediate index) |
| PRFH (scalar plus scalar) | Contiguous prefetch halfwords (scalar index) |
| PRFH (scalar plus vector) | Gather prefetch halfwords (scalar plus vector) |
| PRFH (vector plus immediate) | Gather prefetch halfwords (vector plus immediate) |
| PRFM (immediate) | Prefetch memory (immediate) |
| PRFM (literal) | Prefetch memory (literal) |
| PRFM (register) | Prefetch memory (register) |
| PRFUM | Prefetch memory (unscaled offset) |
| PRFW (scalar plus immediate) | Contiguous prefetch words (immediate index) |
| PRFW (scalar plus scalar) | Contiguous prefetch words (scalar index) |
| PRFW (scalar plus vector) | Gather prefetch words (scalar plus vector) |
| PRFW (vector plus immediate) | Gather prefetch words (vector plus immediate) |
| PSB | Profiling synchronization barrier |
| PSEL | Predicate select between predicate register or all-false |
| PSSBB | Physical speculative store bypass barrier |
| PTEST | Set condition flags for predicate |
| PTRUE (predicate as counter) | Initialise predicate-as-counter to all active |
| PTRUE (predicate) | Initialise predicate from named constraint |
| PTRUES | Initialise predicate from named constraint and set the condition flags |
| PUNPKHI, PUNPKLO | Unpack and widen half of predicate |
| RADDHN, RADDHN2 | Rounding add returning high narrow |
| RADDHNB | Rounding add narrow high part (bottom) |
| RADDHNT | Rounding add narrow high part (top) |
| RAX1 | Bitwise rotate left by 1 and exclusive-OR |
| RAX1 | Rotate and exclusive-OR |
| RBIT | Reverse bits (predicated) |
| RBIT | Reverse bits |
| RBIT (vector) | Reverse bit order (vector) |
| RCWCAS, RCWCASA, RCWCASAL, RCWCASL | Read check write compare and swap doubleword in memory |
| RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL | Read check write compare and swap quadword in memory |
| RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL | Read check write atomic bit clear on doubleword in memory |
| RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL | Read check write atomic bit clear on quadword in memory |
| RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL | Read check write software compare and swap doubleword in memory |
| RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL | Read check write software compare and swap quadword in memory |
| RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL | Read check write software atomic bit clear on doubleword in memory |
| RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL | Read check write software atomic bit clear on quadword in memory |
| RCWSET, RCWSETA, RCWSETAL, RCWSETL | Read check write atomic bit set on doubleword in memory |
| RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL | Read check write atomic bit set on quadword in memory |
| RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL | Read check write software atomic bit set on doubleword in memory |
| RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL | Read check write software atomic bit set on quadword in memory |
| RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL | Read check write software swap doubleword in memory |
| RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL | Read check write software swap quadword in memory |
| RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL | Read check write swap doubleword in memory |
| RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL | Read check write swap quadword in memory |
| RDFFR (predicated) | Return predicate of succesfully loaded elements |
| RDFFR (unpredicated) | Read the first-fault register |
| RDFFRS | Return predicate of succesfully loaded elements, setting the condition flags |
| RDSVL | Read multiple of Streaming SVE vector register size to scalar register |
| RDVL | Read multiple of vector register size to scalar register |
| RET | Return from subroutine |
| RETAA, RETAB | Return from subroutine, with pointer authentication |
| RETAASPPC, RETABSPPC | Return from subroutine, with enhanced pointer authentication using an immediate offset |
| RETAASPPCR, RETABSPPCR | Return from subroutine, with enhanced pointer authentication using a register |
| REV | Reverse bytes |
| REV (predicate) | Reverse all elements in a predicate |
| REV (vector) | Reverse all elements in a vector (unpredicated) |
| REV16 | Reverse bytes in 16-bit halfwords |
| REV16 (vector) | Reverse elements in 16-bit halfwords (vector) |
| REV32 | Reverse bytes in 32-bit words |
| REV32 (vector) | Reverse elements in 32-bit words (vector) |
| REV64 | Reverse elements in 64-bit doublewords (vector) |
| REV64 | Reverse bytes |
| REVB, REVH, REVW | Reverse bytes / halfwords / words within elements (predicated) |
| REVD | Reverse 64-bit doublewords in elements (predicated) |
| RMIF | Rotate, mask insert flags |
| ROR (immediate) | Rotate right (immediate) |
| ROR (register) | Rotate right (register) |
| RORV | Rotate right variable |
| RPRFM | Range prefetch memory |
| RSHRN, RSHRN2 | Rounding shift right narrow (immediate) |
| RSHRNB | Rounding shift right narrow by immediate (bottom) |
| RSHRNT | Rounding shift right narrow by immediate (top) |
| RSUBHN, RSUBHN2 | Rounding subtract returning high narrow |
| RSUBHNB | Rounding subtract narrow high part (bottom) |
| RSUBHNT | Rounding subtract narrow high part (top) |
| SABA | Signed absolute difference and accumulate |
| SABA | Signed absolute difference and accumulate |
| SABAL, SABAL2 | Signed absolute difference and accumulate long |
| SABALB | Signed absolute difference and accumulate long (bottom) |
| SABALT | Signed absolute difference and accumulate long (top) |
| SABD | Signed absolute difference (predicated) |
| SABD | Signed absolute difference |
| SABDL, SABDL2 | Signed absolute difference long |
| SABDLB | Signed absolute difference long (bottom) |
| SABDLT | Signed absolute difference long (top) |
| SADALP | Signed add and accumulate long pairwise |
| SADALP | Signed add and accumulate long pairwise |
| SADDL, SADDL2 | Signed add long (vector) |
| SADDLB | Signed add long (bottom) |
| SADDLBT | Signed add long (bottom + top) |
| SADDLP | Signed add long pairwise |
| SADDLT | Signed add long (top) |
| SADDLV | Signed add long across vector |
| SADDV | Signed add reduction to scalar |
| SADDW, SADDW2 | Signed add wide |
| SADDWB | Signed add wide (bottom) |
| SADDWT | Signed add wide (top) |
| SB | Speculation barrier |
| SBC | Subtract with carry |
| SBCLB | Subtract with carry long (bottom) |
| SBCLT | Subtract with carry long (top) |
| SBCS | Subtract with carry, setting flags |
| SBFIZ | Signed bitfield insert in zeros |
| SBFM | Signed bitfield move |
| SBFX | Signed bitfield extract |
| SCLAMP | Multi-vector signed clamp to minimum/maximum vector |
| SCLAMP | Signed clamp to minimum/maximum vector |
| SCVTF | Multi-vector signed integer convert to floating-point |
| SCVTF (predicated) | Signed integer convert to floating-point (predicated) |
| SCVTF (scalar SIMD&FP) | Signed integer convert to floating-point (scalar SIMD&FP) |
| SCVTF (scalar, fixed-point) | Signed fixed-point convert to floating-point (scalar) |
| SCVTF (scalar, integer) | Signed integer convert to floating-point (scalar) |
| SCVTF (vector, fixed-point) | Signed fixed-point convert to floating-point (vector) |
| SCVTF (vector, integer) | Signed integer convert to floating-point (vector) |
| SDIV | Signed divide (predicated) |
| SDIV | Signed divide |
| SDIVR | Signed reversed divide (predicated) |
| SDOT (2-way, indexed) | Signed integer indexed dot product |
| SDOT (2-way, multiple and indexed vector) | Multi-vector signed integer dot-product by indexed element |
| SDOT (2-way, multiple and single vector) | Multi-vector signed integer dot-product by vector |
| SDOT (2-way, multiple vectors) | Multi-vector signed integer dot-product |
| SDOT (2-way, vectors) | Signed integer dot product |
| SDOT (4-way, indexed) | Signed integer indexed dot product |
| SDOT (4-way, multiple and indexed vector) | Multi-vector signed integer dot-product by indexed element |
| SDOT (4-way, multiple and single vector) | Multi-vector signed integer dot-product by vector |
| SDOT (4-way, multiple vectors) | Multi-vector signed integer dot-product |
| SDOT (4-way, vectors) | Signed integer dot product |
| SDOT (by element) | Dot product signed arithmetic (vector, by element) |
| SDOT (vector) | Dot product signed arithmetic (vector) |
| SEL | Multi-vector conditionally select elements from two vectors |
| SEL (predicates) | Conditionally select elements from two predicates |
| SEL (vectors) | Conditionally select elements from two vectors |
| SETF8, SETF16 | Evaluation of 8-bit or 16-bit flag values |
| SETFFR | Initialise the first-fault register to all true |
| SETGP, SETGM, SETGE | Memory set with tag setting |
| SETGPN, SETGMN, SETGEN | Memory set with tag setting, non-temporal |
| SETGPT, SETGMT, SETGET | Memory set with tag setting, unprivileged |
| SETGPTN, SETGMTN, SETGETN | Memory set with tag setting, unprivileged and non-temporal |
| SETP, SETM, SETE | Memory set |
| SETPN, SETMN, SETEN | Memory set, non-temporal |
| SETPT, SETMT, SETET | Memory set, unprivileged |
| SETPTN, SETMTN, SETETN | Memory set, unprivileged and non-temporal |
| SEV | Send event |
| SEVL | Send event local |
| SHA1C | SHA1 hash update (choose) |
| SHA1H | SHA1 fixed rotate |
| SHA1M | SHA1 hash update (majority) |
| SHA1P | SHA1 hash update (parity) |
| SHA1SU0 | SHA1 schedule update 0 |
| SHA1SU1 | SHA1 schedule update 1 |
| SHA256H | SHA256 hash update (part 1) |
| SHA256H2 | SHA256 hash update (part 2) |
| SHA256SU0 | SHA256 schedule update 0 |
| SHA256SU1 | SHA256 schedule update 1 |
| SHA512H | SHA512 hash update part 1 |
| SHA512H2 | SHA512 hash update part 2 |
| SHA512SU0 | SHA512 schedule update 0 |
| SHA512SU1 | SHA512 schedule update 1 |
| SHADD | Signed halving add |
| SHADD | Signed halving addition |
| Shared Pseudocode Functions | |
| SHL | Shift left (immediate) |
| SHLL, SHLL2 | Shift left long (by element size) |
| SHRN, SHRN2 | Shift right narrow (immediate) |
| SHRNB | Shift right narrow by immediate (bottom) |
| SHRNT | Shift right narrow by immediate (top) |
| SHSUB | Signed halving subtract |
| SHSUB | Signed halving subtract |
| SHSUBR | Signed halving subtract reversed vectors |
| SLI | Shift left and insert (immediate) |
| SLI | Shift left and insert (immediate) |
| SM3PARTW1 | SM3PARTW1 |
| SM3PARTW2 | SM3PARTW2 |
| SM3SS1 | SM3SS1 |
| SM3TT1A | SM3TT1A |
| SM3TT1B | SM3TT1B |
| SM3TT2A | SM3TT2A |
| SM3TT2B | SM3TT2B |
| SM4E | SM4 encode |
| SM4E | SM4 encryption and decryption |
| SM4EKEY | SM4 key |
| SM4EKEY | SM4 key updates |
| SMADDL | Signed multiply-add long |
| SMAX | Signed maximum (vector) |
| SMAX (immediate) | Signed maximum (immediate) |
| SMAX (immediate) | Signed maximum with immediate (unpredicated) |
| SMAX (multiple and single vector) | Multi-vector signed maximum by vector |
| SMAX (multiple vectors) | Multi-vector signed maximum |
| SMAX (register) | Signed maximum (register) |
| SMAX (vectors) | Signed maximum vectors (predicated) |
| SMAXP | Signed maximum pairwise |
| SMAXP | Signed maximum pairwise |
| SMAXQV | Signed maximum reduction of quadword vector segments |
| SMAXV | Signed maximum across vector |
| SMAXV | Signed maximum reduction to scalar |
| SMC | Secure monitor call |
| SMIN | Signed minimum (vector) |
| SMIN (immediate) | Signed minimum (immediate) |
| SMIN (immediate) | Signed minimum with immediate (unpredicated) |
| SMIN (multiple and single vector) | Multi-vector signed minimum by vector |
| SMIN (multiple vectors) | Multi-vector signed minimum |
| SMIN (register) | Signed minimum (register) |
| SMIN (vectors) | Signed minimum vectors (predicated) |
| SMINP | Signed minimum pairwise |
| SMINP | Signed minimum pairwise |
| SMINQV | Signed minimum reduction of quadword vector segments |
| SMINV | Signed minimum reduction to scalar |
| SMINV | Signed minimum across vector |
| SMLAL (multiple and indexed vector) | Multi-vector signed integer multiply-add long by indexed element |
| SMLAL (multiple and single vector) | Multi-vector signed integer multiply-add long by vector |
| SMLAL (multiple vectors) | Multi-vector signed integer multiply-add long |
| SMLAL, SMLAL2 (by element) | Signed multiply-add long (vector, by element) |
| SMLAL, SMLAL2 (vector) | Signed multiply-add long (vector) |
| SMLALB (indexed) | Signed multiply-add long to accumulator (bottom, indexed) |
| SMLALB (vectors) | Signed multiply-add long to accumulator (bottom) |
| SMLALL (multiple and indexed vector) | Multi-vector signed integer multiply-add long-long by indexed element |
| SMLALL (multiple and single vector) | Multi-vector signed integer multiply-add long-long by vector |
| SMLALL (multiple vectors) | Multi-vector signed integer multiply-add long-long |
| SMLALT (indexed) | Signed multiply-add long to accumulator (top, indexed) |
| SMLALT (vectors) | Signed multiply-add long to accumulator (top) |
| SMLSL (multiple and indexed vector) | Multi-vector signed integer multiply-subtract long by indexed element |
| SMLSL (multiple and single vector) | Multi-vector signed integer multiply-subtract long by vector |
| SMLSL (multiple vectors) | Multi-vector signed integer multiply-subtract long |
| SMLSL, SMLSL2 (by element) | Signed multiply-subtract long (vector, by element) |
| SMLSL, SMLSL2 (vector) | Signed multiply-subtract long (vector) |
| SMLSLB (indexed) | Signed multiply-subtract long from accumulator (bottom, indexed) |
| SMLSLB (vectors) | Signed multiply-subtract long from accumulator (bottom) |
| SMLSLL (multiple and indexed vector) | Multi-vector signed integer multiply-subtract long-long by indexed element |
| SMLSLL (multiple and single vector) | Multi-vector signed integer multiply-subtract long-long by vector |
| SMLSLL (multiple vectors) | Multi-vector signed integer multiply-subtract long-long |
| SMLSLT (indexed) | Signed multiply-subtract long from accumulator (top, indexed) |
| SMLSLT (vectors) | Signed multiply-subtract long from accumulator (top) |
| SMMLA | Signed 8-bit integer matrix multiply-accumulate to 32-bit integer |
| SMMLA (vector) | Signed 8-bit integer matrix multiply-accumulate (vector) |
| SMNEGL | Signed multiply-negate long |
| SMOP4A (2-way) | Signed integer quarter-tile sums of two outer products, accumulating |
| SMOP4A (4-way) | Signed integer quarter-tile sums of four outer products, accumulating |
| SMOP4S (2-way) | Signed integer quarter-tile sums of two outer products, subtracting |
| SMOP4S (4-way) | Signed integer quarter-tile sums of four outer products, subtracting |
| SMOPA (2-way) | Signed integer sum of outer products and accumulate |
| SMOPA (4-way) | Signed integer sum of outer products and accumulate |
| SMOPS (2-way) | Signed integer sum of outer products and subtract |
| SMOPS (4-way) | Signed integer sum of outer products and subtract |
| SMOV | Signed move vector element to general-purpose register |
| SMSTART | Enables access to Streaming SVE mode and SME architectural state |
| SMSTOP | Disables access to Streaming SVE mode and SME architectural state |
| SMSUBL | Signed multiply-subtract long |
| SMULH | Signed multiply high |
| SMULH (predicated) | Signed multiply returning high half (predicated) |
| SMULH (unpredicated) | Signed multiply returning high half (unpredicated) |
| SMULL | Signed multiply long |
| SMULL, SMULL2 (by element) | Signed multiply long (vector, by element) |
| SMULL, SMULL2 (vector) | Signed multiply long (vector) |
| SMULLB (indexed) | Signed multiply long (bottom, indexed) |
| SMULLB (vectors) | Signed multiply long (bottom) |
| SMULLT (indexed) | Signed multiply long (top, indexed) |
| SMULLT (vectors) | Signed multiply long (top) |
| SPLICE | Splice two vectors under predicate control |
| SQABS | Signed saturating absolute value |
| SQABS | Signed saturating absolute value |
| SQADD | Signed saturating add |
| SQADD (immediate) | Signed saturating add immediate (unpredicated) |
| SQADD (vectors, predicated) | Signed saturating addition (predicated) |
| SQADD (vectors, unpredicated) | Signed saturating add vectors (unpredicated) |
| SQCADD | Saturating complex integer add with rotate |
| SQCVT (four registers) | Multi-vector signed saturating extract narrow |
| SQCVT (two registers) | Multi-vector signed saturating extract narrow |
| SQCVTN | Multi-vector signed saturating extract narrow and interleave |
| SQCVTN | Signed 32-bit integer saturating extract narrow and interleave to 16-bit integer |
| SQCVTU (four registers) | Multi-vector signed saturating unsigned extract narrow |
| SQCVTU (two registers) | Multi-vector signed saturating unsigned extract narrow |
| SQCVTUN | Signed 32-bit integer saturating unsigned extract narrow and interleave to 16-bit integer |
| SQCVTUN | Multi-vector signed saturating unsigned extract narrow and interleave |
| SQDECB | Signed saturating decrement scalar by multiple of 8-bit predicate constraint element count |
| SQDECD (scalar) | Signed saturating decrement scalar by multiple of 64-bit predicate constraint element count |
| SQDECD (vector) | Signed saturating decrement vector by multiple of 64-bit predicate constraint element count |
| SQDECH (scalar) | Signed saturating decrement scalar by multiple of 16-bit predicate constraint element count |
| SQDECH (vector) | Signed saturating decrement vector by multiple of 16-bit predicate constraint element count |
| SQDECP (scalar) | Signed saturating decrement scalar by count of true predicate elements |
| SQDECP (vector) | Signed saturating decrement vector by count of true predicate elements |
| SQDECW (scalar) | Signed saturating decrement scalar by multiple of 32-bit predicate constraint element count |
| SQDECW (vector) | Signed saturating decrement vector by multiple of 32-bit predicate constraint element count |
| SQDMLAL, SQDMLAL2 (by element) | Signed saturating doubling multiply-add long (by element) |
| SQDMLAL, SQDMLAL2 (vector) | Signed saturating doubling multiply-add long |
| SQDMLALB (indexed) | Signed saturating doubling multiply-add long to accumulator (bottom, indexed) |
| SQDMLALB (vectors) | Signed saturating doubling multiply-add long to accumulator (bottom) |
| SQDMLALBT | Signed saturating doubling multiply-add long to accumulator (bottom × top) |
| SQDMLALT (indexed) | Signed saturating doubling multiply-add long to accumulator (top, indexed) |
| SQDMLALT (vectors) | Signed saturating doubling multiply-add long to accumulator (top) |
| SQDMLSL, SQDMLSL2 (by element) | Signed saturating doubling multiply-subtract long (by element) |
| SQDMLSL, SQDMLSL2 (vector) | Signed saturating doubling multiply-subtract long |
| SQDMLSLB (indexed) | Signed saturating doubling multiply-subtract long from accumulator (bottom, indexed) |
| SQDMLSLB (vectors) | Signed saturating doubling multiply-subtract long from accumulator (bottom) |
| SQDMLSLBT | Signed saturating doubling multiply-subtract long from accumulator (bottom × top) |
| SQDMLSLT (indexed) | Signed saturating doubling multiply-subtract long from accumulator (top, indexed) |
| SQDMLSLT (vectors) | Signed saturating doubling multiply-subtract long from accumulator (top) |
| SQDMULH (by element) | Signed saturating doubling multiply returning high half (by element) |
| SQDMULH (indexed) | Signed saturating doubling multiply high (indexed) |
| SQDMULH (multiple and single vector) | Multi-vector signed saturating doubling multiply high by vector |
| SQDMULH (multiple vectors) | Multi-vector signed saturating doubling multiply high |
| SQDMULH (vector) | Signed saturating doubling multiply returning high half |
| SQDMULH (vectors) | Signed saturating doubling multiply high (unpredicated) |
| SQDMULL, SQDMULL2 (by element) | Signed saturating doubling multiply long (by element) |
| SQDMULL, SQDMULL2 (vector) | Signed saturating doubling multiply long |
| SQDMULLB (indexed) | Signed saturating doubling multiply long (bottom, indexed) |
| SQDMULLB (vectors) | Signed saturating doubling multiply long (bottom) |
| SQDMULLT (indexed) | Signed saturating doubling multiply long (top, indexed) |
| SQDMULLT (vectors) | Signed saturating doubling multiply long (top) |
| SQINCB | Signed saturating increment scalar by multiple of 8-bit predicate constraint element count |
| SQINCD (scalar) | Signed saturating increment scalar by multiple of 64-bit predicate constraint element count |
| SQINCD (vector) | Signed saturating increment vector by multiple of 64-bit predicate constraint element count |
| SQINCH (scalar) | Signed saturating increment scalar by multiple of 16-bit predicate constraint element count |
| SQINCH (vector) | Signed saturating increment vector by multiple of 16-bit predicate constraint element count |
| SQINCP (scalar) | Signed saturating increment scalar by count of true predicate elements |
| SQINCP (vector) | Signed saturating increment vector by count of true predicate elements |
| SQINCW (scalar) | Signed saturating increment scalar by multiple of 32-bit predicate constraint element count |
| SQINCW (vector) | Signed saturating increment vector by multiple of 32-bit predicate constraint element count |
| SQNEG | Signed saturating negate |
| SQNEG | Signed saturating negate |
| SQRDCMLAH (indexed) | Saturating rounding doubling complex integer multiply-add high with rotate (indexed) |
| SQRDCMLAH (vectors) | Saturating rounding doubling complex integer multiply-add high with rotate |
| SQRDMLAH (by element) | Signed saturating rounding doubling multiply accumulate returning high half (by element) |
| SQRDMLAH (indexed) | Signed saturating rounding doubling multiply-add high to accumulator (indexed) |
| SQRDMLAH (vector) | Signed saturating rounding doubling multiply accumulate returning high half (vector) |
| SQRDMLAH (vectors) | Signed saturating rounding doubling multiply-add high to accumulator (unpredicated) |
| SQRDMLSH (by element) | Signed saturating rounding doubling multiply subtract returning high half (by element) |
| SQRDMLSH (indexed) | Signed saturating rounding doubling multiply-subtract high from accumulator (indexed) |
| SQRDMLSH (vector) | Signed saturating rounding doubling multiply subtract returning high half (vector) |
| SQRDMLSH (vectors) | Signed saturating rounding doubling multiply-subtract high from accumulator (unpredicated) |
| SQRDMULH (by element) | Signed saturating rounding doubling multiply returning high half (by element) |
| SQRDMULH (indexed) | Signed saturating rounding doubling multiply high (indexed) |
| SQRDMULH (vector) | Signed saturating rounding doubling multiply returning high half |
| SQRDMULH (vectors) | Signed saturating rounding doubling multiply high (unpredicated) |
| SQRSHL | Signed saturating rounding shift left by vector (predicated) |
| SQRSHL | Signed saturating rounding shift left (register) |
| SQRSHLR | Signed saturating rounding shift left reversed vectors (predicated) |
| SQRSHR (four registers) | Multi-vector signed saturating rounding shift right narrow by immediate |
| SQRSHR (two registers) | Multi-vector signed saturating rounding shift right narrow by immediate |
| SQRSHRN | Multi-vector signed saturating rounding shift right narrow by immediate and interleave |
| SQRSHRN | Signed saturating rounding shift right narrow by immediate and interleave |
| SQRSHRN, SQRSHRN2 | Signed saturating rounded shift right narrow (immediate) |
| SQRSHRNB | Signed saturating rounding shift right narrow by immediate (bottom) |
| SQRSHRNT | Signed saturating rounding shift right narrow by immediate (top) |
| SQRSHRU (four registers) | Multi-vector signed saturating rounding shift right unsigned narrow by immediate |
| SQRSHRU (two registers) | Multi-vector signed saturating rounding shift right unsigned narrow by immediate |
| SQRSHRUN | Signed saturating rounding shift right unsigned narrow by immediate and interleave |
| SQRSHRUN | Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave |
| SQRSHRUN, SQRSHRUN2 | Signed saturating rounded shift right unsigned narrow (immediate) |
| SQRSHRUNB | Signed saturating rounding shift right unsigned narrow by immediate (bottom) |
| SQRSHRUNT | Signed saturating rounding shift right unsigned narrow by immediate (top) |
| SQSHL (immediate) | Signed saturating shift left by immediate |
| SQSHL (immediate) | Signed saturating shift left (immediate) |
| SQSHL (register) | Signed saturating shift left (register) |
| SQSHL (vectors) | Signed saturating shift left by vector (predicated) |
| SQSHLR | Signed saturating shift left reversed vectors (predicated) |
| SQSHLU | Signed saturating shift left unsigned (immediate) |
| SQSHLU | Signed saturating shift left unsigned by immediate |
| SQSHRN, SQSHRN2 | Signed saturating shift right narrow (immediate) |
| SQSHRNB | Signed saturating shift right narrow by immediate (bottom) |
| SQSHRNT | Signed saturating shift right narrow by immediate (top) |
| SQSHRUN, SQSHRUN2 | Signed saturating shift right unsigned narrow (immediate) |
| SQSHRUNB | Signed saturating shift right unsigned narrow by immediate (bottom) |
| SQSHRUNT | Signed saturating shift right unsigned narrow by immediate (top) |
| SQSUB | Signed saturating subtract |
| SQSUB (immediate) | Signed saturating subtract immediate (unpredicated) |
| SQSUB (vectors, predicated) | Signed saturating subtraction (predicated) |
| SQSUB (vectors, unpredicated) | Signed saturating subtract vectors (unpredicated) |
| SQSUBR | Signed saturating subtraction reversed vectors (predicated) |
| SQXTN, SQXTN2 | Signed saturating extract narrow |
| SQXTNB | Signed saturating extract narrow (bottom) |
| SQXTNT | Signed saturating extract narrow (top) |
| SQXTUN, SQXTUN2 | Signed saturating extract unsigned narrow |
| SQXTUNB | Signed saturating unsigned extract narrow (bottom) |
| SQXTUNT | Signed saturating unsigned extract narrow (top) |
| SRHADD | Signed rounding halving addition |
| SRHADD | Signed rounding halving add |
| SRI | Shift right and insert (immediate) |
| SRI | Shift right and insert (immediate) |
| SRSHL | Signed rounding shift left by vector (predicated) |
| SRSHL | Signed rounding shift left (register) |
| SRSHL (multiple and single vector) | Multi-vector signed rounding shift left by vector |
| SRSHL (multiple vectors) | Multi-vector signed rounding shift left |
| SRSHLR | Signed rounding shift left reversed vectors (predicated) |
| SRSHR | Signed rounding shift right (immediate) |
| SRSHR | Signed rounding shift right by immediate |
| SRSRA | Signed rounding shift right and accumulate (immediate) |
| SRSRA | Signed rounding shift right and accumulate (immediate) |
| SSBB | Speculative store bypass barrier |
| SSHL | Signed shift left (register) |
| SSHLL, SSHLL2 | Signed shift left long (immediate) |
| SSHLLB | Signed shift left long by immediate (bottom) |
| SSHLLT | Signed shift left long by immediate (top) |
| SSHR | Signed shift right (immediate) |
| SSRA | Signed shift right and accumulate (immediate) |
| SSRA | Signed shift right and accumulate (immediate) |
| SSUBL, SSUBL2 | Signed subtract long |
| SSUBLB | Signed subtract long (bottom) |
| SSUBLBT | Signed subtract long (bottom - top) |
| SSUBLT | Signed subtract long (top) |
| SSUBLTB | Signed subtract long (top - bottom) |
| SSUBW, SSUBW2 | Signed subtract wide |
| SSUBWB | Signed subtract wide (bottom) |
| SSUBWT | Signed subtract wide (top) |
| ST1 (multiple structures) | Store multiple single-element structures from one, two, three, or four registers |
| ST1 (single structure) | Store a single-element structure from one lane of one register |
| ST1B (scalar plus immediate, consecutive registers) | Contiguous store of bytes from multiple consecutive vectors (immediate index) |
| ST1B (scalar plus immediate, single register) | Contiguous store bytes from vector (immediate index) |
| ST1B (scalar plus immediate, strided registers) | Contiguous store of bytes from multiple strided vectors (immediate index) |
| ST1B (scalar plus scalar, consecutive registers) | Contiguous store of bytes from multiple consecutive vectors (scalar index) |
| ST1B (scalar plus scalar, single register) | Contiguous store bytes from vector (scalar index) |
| ST1B (scalar plus scalar, strided registers) | Contiguous store of bytes from multiple strided vectors (scalar index) |
| ST1B (scalar plus scalar, tile slice) | Contiguous store of bytes from 8-bit element ZA tile slice |
| ST1B (scalar plus vector) | Scatter store bytes from a vector (vector index) |
| ST1B (vector plus immediate) | Scatter store bytes from a vector (immediate index) |
| ST1D (scalar plus immediate, consecutive registers) | Contiguous store of doublewords from multiple consecutive vectors (immediate index) |
| ST1D (scalar plus immediate, single register) | Contiguous store doublewords from vector (immediate index) |
| ST1D (scalar plus immediate, strided registers) | Contiguous store of doublewords from multiple strided vectors (immediate index) |
| ST1D (scalar plus scalar, consecutive registers) | Contiguous store of doublewords from multiple consecutive vectors (scalar index) |
| ST1D (scalar plus scalar, single register) | Contiguous store doublewords from vector (scalar index) |
| ST1D (scalar plus scalar, strided registers) | Contiguous store of doublewords from multiple strided vectors (scalar index) |
| ST1D (scalar plus scalar, tile slice) | Contiguous store of doublewords from 64-bit element ZA tile slice |
| ST1D (scalar plus vector) | Scatter store doublewords from a vector (vector index) |
| ST1D (vector plus immediate) | Scatter store doublewords from a vector (immediate index) |
| ST1H (scalar plus immediate, consecutive registers) | Contiguous store of halfwords from multiple consecutive vectors (immediate index) |
| ST1H (scalar plus immediate, single register) | Contiguous store halfwords from vector (immediate index) |
| ST1H (scalar plus immediate, strided registers) | Contiguous store of halfwords from multiple strided vectors (immediate index) |
| ST1H (scalar plus scalar, consecutive registers) | Contiguous store of halfwords from multiple consecutive vectors (scalar index) |
| ST1H (scalar plus scalar, single register) | Contiguous store halfwords from vector (scalar index) |
| ST1H (scalar plus scalar, strided registers) | Contiguous store of halfwords from multiple strided vectors (scalar index) |
| ST1H (scalar plus scalar, tile slice) | Contiguous store of halfwords from 16-bit element ZA tile slice |
| ST1H (scalar plus vector) | Scatter store halfwords from a vector (vector index) |
| ST1H (vector plus immediate) | Scatter store halfwords from a vector (immediate index) |
| ST1Q | Scatter store quadwords |
| ST1Q | Contiguous store of quadwords from 128-bit element ZA tile slice |
| ST1W (scalar plus immediate, consecutive registers) | Contiguous store of words from multiple consecutive vectors (immediate index) |
| ST1W (scalar plus immediate, single register) | Contiguous store words from vector (immediate index) |
| ST1W (scalar plus immediate, strided registers) | Contiguous store of words from multiple strided vectors (immediate index) |
| ST1W (scalar plus scalar, consecutive registers) | Contiguous store of words from multiple consecutive vectors (scalar index) |
| ST1W (scalar plus scalar, single register) | Contiguous store words from vector (scalar index) |
| ST1W (scalar plus scalar, strided registers) | Contiguous store of words from multiple strided vectors (scalar index) |
| ST1W (scalar plus scalar, tile slice) | Contiguous store of words from 32-bit element ZA tile slice |
| ST1W (scalar plus vector) | Scatter store words from a vector (vector index) |
| ST1W (vector plus immediate) | Scatter store words from a vector (immediate index) |
| ST2 (multiple structures) | Store multiple 2-element structures from two registers |
| ST2 (single structure) | Store single 2-element structure from one lane of two registers |
| ST2B (scalar plus immediate) | Contiguous store two-byte structures from two vectors (immediate index) |
| ST2B (scalar plus scalar) | Contiguous store two-byte structures from two vectors (scalar index) |
| ST2D (scalar plus immediate) | Contiguous store two-doubleword structures from two vectors (immediate index) |
| ST2D (scalar plus scalar) | Contiguous store two-doubleword structures from two vectors (scalar index) |
| ST2G | Store Allocation Tags |
| ST2H (scalar plus immediate) | Contiguous store two-halfword structures from two vectors (immediate index) |
| ST2H (scalar plus scalar) | Contiguous store two-halfword structures from two vectors (scalar index) |
| ST2Q (scalar plus immediate) | Contiguous store two-quadword structures from two vectors (immediate index) |
| ST2Q (scalar plus scalar) | Contiguous store two-quadword structures from two vectors (scalar index) |
| ST2W (scalar plus immediate) | Contiguous store two-word structures from two vectors (immediate index) |
| ST2W (scalar plus scalar) | Contiguous store two-word structures from two vectors (scalar index) |
| ST3 (multiple structures) | Store multiple 3-element structures from three registers |
| ST3 (single structure) | Store single 3-element structure from one lane of three registers |
| ST3B (scalar plus immediate) | Contiguous store three-byte structures from three vectors (immediate index) |
| ST3B (scalar plus scalar) | Contiguous store three-byte structures from three vectors (scalar index) |
| ST3D (scalar plus immediate) | Contiguous store three-doubleword structures from three vectors (immediate index) |
| ST3D (scalar plus scalar) | Contiguous store three-doubleword structures from three vectors (scalar index) |
| ST3H (scalar plus immediate) | Contiguous store three-halfword structures from three vectors (immediate index) |
| ST3H (scalar plus scalar) | Contiguous store three-halfword structures from three vectors (scalar index) |
| ST3Q (scalar plus immediate) | Contiguous store three-quadword structures from three vectors (immediate index) |
| ST3Q (scalar plus scalar) | Contiguous store three-quadword structures from three vectors (scalar index) |
| ST3W (scalar plus immediate) | Contiguous store three-word structures from three vectors (immediate index) |
| ST3W (scalar plus scalar) | Contiguous store three-word structures from three vectors (scalar index) |
| ST4 (multiple structures) | Store multiple 4-element structures from four registers |
| ST4 (single structure) | Store single 4-element structure from one lane of four registers |
| ST4B (scalar plus immediate) | Contiguous store four-byte structures from four vectors (immediate index) |
| ST4B (scalar plus scalar) | Contiguous store four-byte structures from four vectors (scalar index) |
| ST4D (scalar plus immediate) | Contiguous store four-doubleword structures from four vectors (immediate index) |
| ST4D (scalar plus scalar) | Contiguous store four-doubleword structures from four vectors (scalar index) |
| ST4H (scalar plus immediate) | Contiguous store four-halfword structures from four vectors (immediate index) |
| ST4H (scalar plus scalar) | Contiguous store four-halfword structures from four vectors (scalar index) |
| ST4Q (scalar plus immediate) | Contiguous store four-quadword structures from four vectors (immediate index) |
| ST4Q (scalar plus scalar) | Contiguous store four-quadword structures from four vectors (scalar index) |
| ST4W (scalar plus immediate) | Contiguous store four-word structures from four vectors (immediate index) |
| ST4W (scalar plus scalar) | Contiguous store four-word structures from four vectors (scalar index) |
| ST64B | Single-copy atomic 64-byte store without status result |
| ST64BV | Single-copy atomic 64-byte store with status result |
| ST64BV0 | Single-copy atomic 64-byte EL0 store with status result |
| STADD, STADDL | Atomic add on word or doubleword in memory, without return |
| STADDB, STADDLB | Atomic add on byte in memory, without return |
| STADDH, STADDLH | Atomic add on halfword in memory, without return |
| STBFADD, STBFADDL | BFloat16 floating-point atomic add in memory, without return |
| STBFMAX, STBFMAXL | BFloat16 floating-point atomic maximum in memory, without return |
| STBFMAXNM, STBFMAXNML | BFloat16 floating-point atomic maximum number in memory, without return |
| STBFMIN, STBFMINL | BFloat16 floating-point atomic minimum in memory, without return |
| STBFMINNM, STBFMINNML | BFloat16 floating-point atomic minimum number in memory, without return |
| STCLR, STCLRL | Atomic bit clear on word or doubleword in memory, without return |
| STCLRB, STCLRLB | Atomic bit clear on byte in memory, without return |
| STCLRH, STCLRLH | Atomic bit clear on halfword in memory, without return |
| STEOR, STEORL | Atomic exclusive-OR on word or doubleword in memory, without return |
| STEORB, STEORLB | Atomic exclusive-OR on byte in memory, without return |
| STEORH, STEORLH | Atomic exclusive-OR on halfword in memory, without return |
| STFADD, STFADDL | Floating-point atomic add in memory, without return |
| STFMAX, STFMAXL | Floating-point atomic maximum in memory, without return |
| STFMAXNM, STFMAXNML | Floating-point atomic maximum number in memory, without return |
| STFMIN, STFMINL | Floating-point atomic minimum in memory, without return |
| STFMINNM, STFMINNML | Floating-point atomic minimum number in memory, without return |
| STG | Store Allocation Tag |
| STGM | Store Allocation Tag multiple |
| STGP | Store Allocation Tag and pair of registers |
| STILP | Store-release ordered pair of registers |
| STL1 (SIMD&FP) | Store-release a single-element structure from one lane of one register |
| STLLR | Store LORelease register |
| STLLRB | Store LORelease register byte |
| STLLRH | Store LORelease register halfword |
| STLR | Store-release register |
| STLRB | Store-release register byte |
| STLRH | Store-release register halfword |
| STLTXR | Store-release unprivileged exclusive register |
| STLUR | Store-release register (unscaled) |
| STLUR (SIMD&FP) | Store-release SIMD&FP register (unscaled offset) |
| STLURB | Store-release register byte (unscaled) |
| STLURH | Store-release register halfword (unscaled) |
| STLXP | Store-release exclusive pair of registers |
| STLXR | Store-release exclusive register |
| STLXRB | Store-release exclusive register byte |
| STLXRH | Store-release exclusive register halfword |
| STMOPA (2-way) | Signed integer sparse sum of two outer products, accumulating |
| STMOPA (4-way) | Signed integer sparse sum of four outer products, accumulating |
| STNP | Store pair of registers, with non-temporal hint |
| STNP (SIMD&FP) | Store pair of SIMD&FP registers, with non-temporal hint |
| STNT1B (scalar plus immediate, consecutive registers) | Contiguous store non-temporal of bytes from multiple consecutive vectors (immediate index) |
| STNT1B (scalar plus immediate, single register) | Contiguous store non-temporal bytes from vector (immediate index) |
| STNT1B (scalar plus immediate, strided registers) | Contiguous store non-temporal of bytes from multiple strided vectors (immediate index) |
| STNT1B (scalar plus scalar, consecutive registers) | Contiguous store non-temporal of bytes from multiple consecutive vectors (scalar index) |
| STNT1B (scalar plus scalar, single register) | Contiguous store non-temporal bytes from vector (scalar index) |
| STNT1B (scalar plus scalar, strided registers) | Contiguous store non-temporal of bytes from multiple strided vectors (scalar index) |
| STNT1B (vector plus scalar) | Scatter store non-temporal bytes |
| STNT1D (scalar plus immediate, consecutive registers) | Contiguous store non-temporal of doublewords from multiple consecutive vectors (immediate index) |
| STNT1D (scalar plus immediate, single register) | Contiguous store non-temporal doublewords from vector (immediate index) |
| STNT1D (scalar plus immediate, strided registers) | Contiguous store non-temporal of doublewords from multiple strided vectors (immediate index) |
| STNT1D (scalar plus scalar, consecutive registers) | Contiguous store non-temporal of doublewords from multiple consecutive vectors (scalar index) |
| STNT1D (scalar plus scalar, single register) | Contiguous store non-temporal doublewords from vector (scalar index) |
| STNT1D (scalar plus scalar, strided registers) | Contiguous store non-temporal of doublewords from multiple strided vectors (scalar index) |
| STNT1D (vector plus scalar) | Scatter store non-temporal doublewords |
| STNT1H (scalar plus immediate, consecutive registers) | Contiguous store non-temporal of halfwords from multiple consecutive vectors (immediate index) |
| STNT1H (scalar plus immediate, single register) | Contiguous store non-temporal halfwords from vector (immediate index) |
| STNT1H (scalar plus immediate, strided registers) | Contiguous store non-temporal of halfwords from multiple strided vectors (immediate index) |
| STNT1H (scalar plus scalar, consecutive registers) | Contiguous store non-temporal of halfwords from multiple consecutive vectors (scalar index) |
| STNT1H (scalar plus scalar, single register) | Contiguous store non-temporal halfwords from vector (scalar index) |
| STNT1H (scalar plus scalar, strided registers) | Contiguous store non-temporal of halfwords from multiple strided vectors (scalar index) |
| STNT1H (vector plus scalar) | Scatter store non-temporal halfwords |
| STNT1W (scalar plus immediate, consecutive registers) | Contiguous store non-temporal of words from multiple consecutive vectors (immediate index) |
| STNT1W (scalar plus immediate, single register) | Contiguous store non-temporal words from vector (immediate index) |
| STNT1W (scalar plus immediate, strided registers) | Contiguous store non-temporal of words from multiple strided vectors (immediate index) |
| STNT1W (scalar plus scalar, consecutive registers) | Contiguous store non-temporal of words from multiple consecutive vectors (scalar index) |
| STNT1W (scalar plus scalar, single register) | Contiguous store non-temporal words from vector (scalar index) |
| STNT1W (scalar plus scalar, strided registers) | Contiguous store non-temporal of words from multiple strided vectors (scalar index) |
| STNT1W (vector plus scalar) | Scatter store non-temporal words |
| STP | Store pair of registers |
| STP (SIMD&FP) | Store pair of SIMD&FP registers |
| STR (array vector) | Store ZA array vector |
| STR (immediate) | Store register (immediate) |
| STR (immediate, SIMD&FP) | Store SIMD&FP register (immediate offset) |
| STR (predicate) | Store predicate register |
| STR (register) | Store register (register) |
| STR (register, SIMD&FP) | Store SIMD&FP register (register offset) |
| STR (table) | Store ZT0 register |
| STR (vector) | Store vector register |
| STRB (immediate) | Store register byte (immediate) |
| STRB (register) | Store register byte (register) |
| STRH (immediate) | Store register halfword (immediate) |
| STRH (register) | Store register halfword (register) |
| STSET, STSETL | Atomic bit set on word or doubleword in memory, without return |
| STSETB, STSETLB | Atomic bit set on byte in memory, without return |
| STSETH, STSETLH | Atomic bit set on halfword in memory, without return |
| STSHH | Store shared hint |
| STSMAX, STSMAXL | Atomic signed maximum on word or doubleword in memory, without return |
| STSMAXB, STSMAXLB | Atomic signed maximum on byte in memory, without return |
| STSMAXH, STSMAXLH | Atomic signed maximum on halfword in memory, without return |
| STSMIN, STSMINL | Atomic signed minimum on word or doubleword in memory, without return |
| STSMINB, STSMINLB | Atomic signed minimum on byte in memory, without return |
| STSMINH, STSMINLH | Atomic signed minimum on halfword in memory, without return |
| STTADD, STTADDL | Atomic add unprivileged, without return |
| STTCLR, STTCLRL | Atomic bit clear unprivileged, without return |
| STTNP | Store unprivileged pair of registers, with non-temporal hint |
| STTNP (SIMD&FP) | Store unprivileged pair of SIMD&FP registers, with non-temporal hint |
| STTP | Store unprivileged pair of registers |
| STTP (SIMD&FP) | Store unprivileged pair of SIMD&FP registers |
| STTR | Store register (unprivileged) |
| STTRB | Store register byte (unprivileged) |
| STTRH | Store register halfword (unprivileged) |
| STTSET, STTSETL | Atomic bit set unprivileged, without return |
| STTXR | Store unprivileged exclusive register |
| STUMAX, STUMAXL | Atomic unsigned maximum on word or doubleword in memory, without return |
| STUMAXB, STUMAXLB | Atomic unsigned maximum on byte in memory, without return |
| STUMAXH, STUMAXLH | Atomic unsigned maximum on halfword in memory, without return |
| STUMIN, STUMINL | Atomic unsigned minimum on word or doubleword in memory, without return |
| STUMINB, STUMINLB | Atomic unsigned minimum on byte in memory, without return |
| STUMINH, STUMINLH | Atomic unsigned minimum on halfword in memory, without return |
| STUR | Store register (unscaled) |
| STUR (SIMD&FP) | Store SIMD&FP register (unscaled offset) |
| STURB | Store register byte (unscaled) |
| STURH | Store register halfword (unscaled) |
| STXP | Store exclusive pair of registers |
| STXR | Store exclusive register |
| STXRB | Store exclusive register byte |
| STXRH | Store exclusive register halfword |
| STZ2G | Store Allocation Tags, zeroing |
| STZG | Store Allocation Tag, zeroing |
| STZGM | Store Allocation Tag and zero multiple |
| SUB (array accumulators) | Subtract multi-vector from ZA array vector accumulators |
| SUB (array results, multiple and single vector) | Subtract replicated single vector from multi-vector with ZA array vector results |
| SUB (array results, multiple vectors) | Subtract multi-vector from multi-vector with ZA array vector results |
| SUB (extended register) | Subtract extended and scaled register |
| SUB (immediate) | Subtract immediate value |
| SUB (immediate) | Subtract immediate (unpredicated) |
| SUB (shifted register) | Subtract optionally-shifted register |
| SUB (vector) | Subtract (vector) |
| SUB (vectors, predicated) | Subtract vectors (predicated) |
| SUB (vectors, unpredicated) | Subtract vectors (unpredicated) |
| SUBG | Subtract with tag |
| SUBHN, SUBHN2 | Subtract returning high narrow |
| SUBHNB | Subtract narrow high part (bottom) |
| SUBHNT | Subtract narrow high part (top) |
| SUBP | Subtract pointer |
| SUBPS | Subtract pointer, setting flags |
| SUBPT | Subtract checked pointer |
| SUBPT (predicated) | Subtract checked pointer vectors (predicated) |
| SUBPT (unpredicated) | Subtract checked pointer vectors (unpredicated) |
| SUBR (immediate) | Reversed subtract from immediate (unpredicated) |
| SUBR (vectors) | Reversed subtract vectors (predicated) |
| SUBS (extended register) | Subtract extended and scaled register, setting flags |
| SUBS (immediate) | Subtract immediate value, setting flags |
| SUBS (shifted register) | Subtract optionally-shifted register, setting flags |
| SUDOT | Signed by unsigned 8-bit integer indexed dot product to 32-bit integer |
| SUDOT (4-way, multiple and indexed vector) | Multi-vector signed by unsigned integer dot-product by indexed elements |
| SUDOT (4-way, multiple and single vector) | Multi-vector signed by unsigned integer dot-product by vector |
| SUDOT (by element) | Dot product with signed and unsigned integers (vector, by element) |
| SUMLALL (multiple and indexed vector) | Multi-vector signed by unsigned integer multiply-add long-long by indexed element |
| SUMLALL (multiple and single vector) | Multi-vector signed by unsigned integer multiply-add long-long by vector |
| SUMOP4A | Signed by unsigned integer quarter-tile sums of four outer products, accumulating |
| SUMOP4S | Signed by unsigned integer quarter-tile sums of four outer products, subtracting |
| SUMOPA (4-way) | Signed by unsigned integer sum of outer products and accumulate |
| SUMOPS | Signed by unsigned integer sum of outer products and subtract |
| SUNPK | Unpack and sign-extend multi-vector elements |
| SUNPKHI, SUNPKLO | Signed unpack and extend half of vector |
| SUQADD | Signed saturating addition of unsigned value |
| SUQADD | Signed saturating accumulate of unsigned value |
| SUTMOPA | Signed by unsigned integer sparse sum of four outer products, accumulating |
| SUVDOT | Multi-vector signed by unsigned integer vertical dot-product by indexed element |
| SVC | Supervisor call |
| SVDOT (2-way) | Multi-vector signed integer vertical dot-product by indexed element |
| SVDOT (4-way) | Multi-vector signed integer vertical dot-product by indexed element |
| SWP, SWPA, SWPAL, SWPL | Swap word or doubleword in memory |
| SWPB, SWPAB, SWPALB, SWPLB | Swap byte in memory |
| SWPH, SWPAH, SWPALH, SWPLH | Swap halfword in memory |
| SWPP, SWPPA, SWPPAL, SWPPL | Swap quadword in memory |
| SWPT, SWPTA, SWPTAL, SWPTL | Swap unprivileged |
| SXTB | Signed extend byte |
| SXTB, SXTH, SXTW | Signed byte / halfword / word extend (predicated) |
| SXTH | Sign extend halfword |
| SXTL, SXTL2 | Signed extend long |
| SXTW | Sign extend word |
| SYS | System instruction |
| SYSL | System instruction with result |
| SYSP | 128-bit system instruction |
| TBL | Table vector lookup |
| TBL | Programmable table lookup in one or two vector table (zeroing) |
| TBLQ | Programmable table lookup within each quadword vector segment (zeroing) |
| TBNZ | Test bit and branch if nonzero |
| TBX | Programmable table lookup in single vector table (merging) |
| TBX | Table vector lookup extension |
| TBXQ | Programmable table lookup within each quadword vector segment (merging) |
| TBZ | Test bit and branch if zero |
| TCANCEL | Cancel current transaction |
| TCOMMIT | Commit current transaction |
| TLBI | TLB invalidate operation |
| TLBIP | TLB invalidate pair operation |
| TRCIT | Trace instrumentation |
| TRN1 | Transpose vectors (primary) |
| TRN1, TRN2 (predicates) | Interleave even or odd elements from two predicates |
| TRN1, TRN2 (vectors) | Interleave even or odd elements from two vectors |
| TRN2 | Transpose vectors (secondary) |
| TSB | Trace synchronization barrier |
| TST (immediate) | Test bits (immediate) |
| TST (shifted register) | Test (shifted register) |
| TSTART | Start transaction |
| TTEST | Test transaction state |
| UABA | Unsigned absolute difference and accumulate |
| UABA | Unsigned absolute difference and accumulate |
| UABAL, UABAL2 | Unsigned absolute difference and accumulate long |
| UABALB | Unsigned absolute difference and accumulate long (bottom) |
| UABALT | Unsigned absolute difference and accumulate long (top) |
| UABD | Unsigned absolute difference (vector) |
| UABD | Unsigned absolute difference (predicated) |
| UABDL, UABDL2 | Unsigned absolute difference long |
| UABDLB | Unsigned absolute difference long (bottom) |
| UABDLT | Unsigned absolute difference long (top) |
| UADALP | Unsigned add and accumulate long pairwise |
| UADALP | Unsigned add and accumulate long pairwise |
| UADDL, UADDL2 | Unsigned add long (vector) |
| UADDLB | Unsigned add long (bottom) |
| UADDLP | Unsigned add long pairwise |
| UADDLT | Unsigned add long (top) |
| UADDLV | Unsigned sum long across vector |
| UADDV | Unsigned add reduction to scalar |
| UADDW, UADDW2 | Unsigned add wide |
| UADDWB | Unsigned add wide (bottom) |
| UADDWT | Unsigned add wide (top) |
| UBFIZ | Unsigned bitfield insert in zeros |
| UBFM | Unsigned bitfield move |
| UBFX | Unsigned bitfield extract |
| UCLAMP | Unsigned clamp to minimum/maximum vector |
| UCLAMP | Multi-vector unsigned clamp to minimum/maximum vector |
| UCVTF | Multi-vector unsigned integer convert to floating-point |
| UCVTF (predicated) | Unsigned integer convert to floating-point (predicated) |
| UCVTF (scalar SIMD&FP) | Unsigned integer convert to floating-point (scalar SIMD&FP) |
| UCVTF (scalar, fixed-point) | Unsigned fixed-point convert to floating-point (scalar) |
| UCVTF (scalar, integer) | Unsigned integer convert to floating-point (scalar) |
| UCVTF (vector, fixed-point) | Unsigned fixed-point convert to floating-point (vector) |
| UCVTF (vector, integer) | Unsigned integer convert to floating-point (vector) |
| UDF | Permanently undefined |
| UDIV | Unsigned divide (predicated) |
| UDIV | Unsigned divide |
| UDIVR | Unsigned reversed divide (predicated) |
| UDOT (2-way, indexed) | Unsigned integer indexed dot product |
| UDOT (2-way, multiple and indexed vector) | Multi-vector unsigned integer dot-product by indexed element |
| UDOT (2-way, multiple and single vector) | Multi-vector unsigned integer dot-product by vector |
| UDOT (2-way, multiple vectors) | Multi-vector unsigned integer dot-product |
| UDOT (2-way, vectors) | Unsigned integer dot product |
| UDOT (4-way, indexed) | Unsigned integer indexed dot product |
| UDOT (4-way, multiple and indexed vector) | Multi-vector unsigned integer dot-product by indexed element |
| UDOT (4-way, multiple and single vector) | Multi-vector unsigned integer dot-product by vector |
| UDOT (4-way, multiple vectors) | Multi-vector unsigned integer dot-product |
| UDOT (4-way, vectors) | Unsigned integer dot product |
| UDOT (by element) | Dot product unsigned arithmetic (vector, by element) |
| UDOT (vector) | Dot product unsigned arithmetic (vector) |
| UHADD | Unsigned halving addition |
| UHADD | Unsigned halving add |
| UHSUB | Unsigned halving subtract |
| UHSUB | Unsigned halving subtract |
| UHSUBR | Unsigned halving subtract reversed vectors |
| UMADDL | Unsigned multiply-add long |
| UMAX | Unsigned maximum (vector) |
| UMAX (immediate) | Unsigned maximum (immediate) |
| UMAX (immediate) | Unsigned maximum with immediate (unpredicated) |
| UMAX (multiple and single vector) | Multi-vector unsigned maximum by vector |
| UMAX (multiple vectors) | Multi-vector unsigned maximum |
| UMAX (register) | Unsigned maximum (register) |
| UMAX (vectors) | Unsigned maximum vectors (predicated) |
| UMAXP | Unsigned maximum pairwise |
| UMAXP | Unsigned maximum pairwise |
| UMAXQV | Unsigned maximum reduction of quadword vector segments |
| UMAXV | Unsigned maximum reduction to scalar |
| UMAXV | Unsigned maximum across vector |
| UMIN | Unsigned minimum (vector) |
| UMIN (immediate) | Unsigned minimum (immediate) |
| UMIN (immediate) | Unsigned minimum with immediate (unpredicated) |
| UMIN (multiple and single vector) | Multi-vector unsigned minimum by vector |
| UMIN (multiple vectors) | Multi-vector unsigned minimum |
| UMIN (register) | Unsigned minimum (register) |
| UMIN (vectors) | Unsigned minimum vectors (predicated) |
| UMINP | Unsigned minimum pairwise |
| UMINP | Unsigned minimum pairwise |
| UMINQV | Unsigned minimum reduction of quadword vector segments |
| UMINV | Unsigned minimum across vector |
| UMINV | Unsigned minimum reduction to scalar |
| UMLAL (multiple and indexed vector) | Multi-vector unsigned integer multiply-add long by indexed element |
| UMLAL (multiple and single vector) | Multi-vector unsigned integer multiply-add long by vector |
| UMLAL (multiple vectors) | Multi-vector unsigned integer multiply-add long |
| UMLAL, UMLAL2 (by element) | Unsigned multiply-add long (vector, by element) |
| UMLAL, UMLAL2 (vector) | Unsigned multiply-add long (vector) |
| UMLALB (indexed) | Unsigned multiply-add long to accumulator (bottom, indexed) |
| UMLALB (vectors) | Unsigned multiply-add long to accumulator (bottom) |
| UMLALL (multiple and indexed vector) | Multi-vector unsigned integer multiply-add long-long by indexed element |
| UMLALL (multiple and single vector) | Multi-vector unsigned integer multiply-add long-long by vector |
| UMLALL (multiple vectors) | Multi-vector unsigned integer multiply-add long-long |
| UMLALT (indexed) | Unsigned multiply-add long to accumulator (top, indexed) |
| UMLALT (vectors) | Unsigned multiply-add long to accumulator (top) |
| UMLSL (multiple and indexed vector) | Multi-vector unsigned integer multiply-subtract long by indexed element |
| UMLSL (multiple and single vector) | Multi-vector unsigned integer multiply-subtract long by vector |
| UMLSL (multiple vectors) | Multi-vector unsigned integer multiply-subtract long |
| UMLSL, UMLSL2 (by element) | Unsigned multiply-subtract long (vector, by element) |
| UMLSL, UMLSL2 (vector) | Unsigned multiply-subtract long (vector) |
| UMLSLB (indexed) | Unsigned multiply-subtract long from accumulator (bottom, indexed) |
| UMLSLB (vectors) | Unsigned multiply-subtract long from accumulator (bottom) |
| UMLSLL (multiple and indexed vector) | Multi-vector unsigned integer multiply-subtract long-long by indexed element |
| UMLSLL (multiple and single vector) | Multi-vector unsigned integer multiply-subtract long-long by vector |
| UMLSLL (multiple vectors) | Multi-vector unsigned integer multiply-subtract long-long |
| UMLSLT (indexed) | Unsigned multiply-subtract long from accumulator (top, indexed) |
| UMLSLT (vectors) | Unsigned multiply-subtract long from accumulator (top) |
| UMMLA | Unsigned 8-bit integer matrix multiply-accumulate to 32-bit integer |
| UMMLA (vector) | Unsigned 8-bit integer matrix multiply-accumulate (vector) |
| UMNEGL | Unsigned multiply-negate long |
| UMOP4A (2-way) | Unsigned integer quarter-tile sums of two outer products, accumulating |
| UMOP4A (4-way) | Unsigned integer quarter-tile sums of four outer products, accumulating |
| UMOP4S (2-way) | Unsigned integer quarter-tile sums of two outer products, subtracting |
| UMOP4S (4-way) | Unsigned integer quarter-tile sums of four outer products, subtracting |
| UMOPA (2-way) | Unsigned integer sum of outer products and accumulate |
| UMOPA (4-way) | Unsigned integer sum of outer products and accumulate |
| UMOPS (2-way) | Unsigned integer sum of outer products and subtract |
| UMOPS (4-way) | Unsigned integer sum of outer products and subtract |
| UMOV | Unsigned move vector element to general-purpose register |
| UMSUBL | Unsigned multiply-subtract long |
| UMULH | Unsigned multiply high |
| UMULH (predicated) | Unsigned multiply returning high half (predicated) |
| UMULH (unpredicated) | Unsigned multiply returning high half (unpredicated) |
| UMULL | Unsigned multiply long |
| UMULL, UMULL2 (by element) | Unsigned multiply long (vector, by element) |
| UMULL, UMULL2 (vector) | Unsigned multiply long (vector) |
| UMULLB (indexed) | Unsigned multiply long (bottom, indexed) |
| UMULLB (vectors) | Unsigned multiply long (bottom) |
| UMULLT (indexed) | Unsigned multiply long (top, indexed) |
| UMULLT (vectors) | Unsigned multiply long (top) |
| UQADD | Unsigned saturating add |
| UQADD (immediate) | Unsigned saturating add immediate (unpredicated) |
| UQADD (vectors, predicated) | Unsigned saturating addition (predicated) |
| UQADD (vectors, unpredicated) | Unsigned saturating add vectors (unpredicated) |
| UQCVT (four registers) | Multi-vector unsigned saturating extract narrow |
| UQCVT (two registers) | Multi-vector unsigned saturating extract narrow |
| UQCVTN | Unsigned 32-bit integer saturating extract narrow and interleave to 16-bit integer |
| UQCVTN | Multi-vector unsigned saturating extract narrow and interleave |
| UQDECB | Unsigned saturating decrement scalar by multiple of 8-bit predicate constraint element count |
| UQDECD (scalar) | Unsigned saturating decrement scalar by multiple of 64-bit predicate constraint element count |
| UQDECD (vector) | Unsigned saturating decrement vector by multiple of 64-bit predicate constraint element count |
| UQDECH (scalar) | Unsigned saturating decrement scalar by multiple of 16-bit predicate constraint element count |
| UQDECH (vector) | Unsigned saturating decrement vector by multiple of 16-bit predicate constraint element count |
| UQDECP (scalar) | Unsigned saturating decrement scalar by count of true predicate elements |
| UQDECP (vector) | Unsigned saturating decrement vector by count of true predicate elements |
| UQDECW (scalar) | Unsigned saturating decrement scalar by multiple of 32-bit predicate constraint element count |
| UQDECW (vector) | Unsigned saturating decrement vector by multiple of 32-bit predicate constraint element count |
| UQINCB | Unsigned saturating increment scalar by multiple of 8-bit predicate constraint element count |
| UQINCD (scalar) | Unsigned saturating increment scalar by multiple of 64-bit predicate constraint element count |
| UQINCD (vector) | Unsigned saturating increment vector by multiple of 64-bit predicate constraint element count |
| UQINCH (scalar) | Unsigned saturating increment scalar by multiple of 16-bit predicate constraint element count |
| UQINCH (vector) | Unsigned saturating increment vector by multiple of 16-bit predicate constraint element count |
| UQINCP (scalar) | Unsigned saturating increment scalar by count of true predicate elements |
| UQINCP (vector) | Unsigned saturating increment vector by count of true predicate elements |
| UQINCW (scalar) | Unsigned saturating increment scalar by multiple of 32-bit predicate constraint element count |
| UQINCW (vector) | Unsigned saturating increment vector by multiple of 32-bit predicate constraint element count |
| UQRSHL | Unsigned saturating rounding shift left by vector (predicated) |
| UQRSHL | Unsigned saturating rounding shift left (register) |
| UQRSHLR | Unsigned saturating rounding shift left reversed vectors (predicated) |
| UQRSHR (four registers) | Multi-vector unsigned saturating rounding shift right narrow by immediate |
| UQRSHR (two registers) | Multi-vector unsigned saturating rounding shift right narrow by immediate |
| UQRSHRN | Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave |
| UQRSHRN | Unsigned saturating rounding shift right narrow by immediate and interleave |
| UQRSHRN, UQRSHRN2 | Unsigned saturating rounded shift right narrow (immediate) |
| UQRSHRNB | Unsigned saturating rounding shift right narrow by immediate (bottom) |
| UQRSHRNT | Unsigned saturating rounding shift right narrow by immediate (top) |
| UQSHL (immediate) | Unsigned saturating shift left by immediate |
| UQSHL (immediate) | Unsigned saturating shift left (immediate) |
| UQSHL (register) | Unsigned saturating shift left (register) |
| UQSHL (vectors) | Unsigned saturating shift left by vector (predicated) |
| UQSHLR | Unsigned saturating shift left reversed vectors (predicated) |
| UQSHRN, UQSHRN2 | Unsigned saturating shift right narrow (immediate) |
| UQSHRNB | Unsigned saturating shift right narrow by immediate (bottom) |
| UQSHRNT | Unsigned saturating shift right narrow by immediate (top) |
| UQSUB | Unsigned saturating subtract |
| UQSUB (immediate) | Unsigned saturating subtract immediate (unpredicated) |
| UQSUB (vectors, predicated) | Unsigned saturating subtraction (predicated) |
| UQSUB (vectors, unpredicated) | Unsigned saturating subtract vectors (unpredicated) |
| UQSUBR | Unsigned saturating subtraction reversed vectors (predicated) |
| UQXTN, UQXTN2 | Unsigned saturating extract narrow |
| UQXTNB | Unsigned saturating extract narrow (bottom) |
| UQXTNT | Unsigned saturating extract narrow (top) |
| URECPE | Unsigned reciprocal estimate |
| URECPE | Unsigned reciprocal estimate (predicated) |
| URHADD | Unsigned rounding halving add |
| URHADD | Unsigned rounding halving addition |
| URSHL | Unsigned rounding shift left by vector (predicated) |
| URSHL | Unsigned rounding shift left (register) |
| URSHL (multiple and single vector) | Multi-vector unsigned rounding shift left by vector |
| URSHL (multiple vectors) | Multi-vector unsigned rounding shift left |
| URSHLR | Unsigned rounding shift left reversed vectors (predicated) |
| URSHR | Unsigned rounding shift right by immediate |
| URSHR | Unsigned rounding shift right (immediate) |
| URSQRTE | Unsigned reciprocal square root estimate (predicated) |
| URSQRTE | Unsigned reciprocal square root estimate |
| URSRA | Unsigned rounding shift right and accumulate (immediate) |
| URSRA | Unsigned rounding shift right and accumulate (immediate) |
| USDOT (4-way, multiple and indexed vector) | Multi-vector unsigned by signed integer dot-product by indexed element |
| USDOT (4-way, multiple and single vector) | Multi-vector unsigned by signed integer dot-product by vector |
| USDOT (4-way, multiple vectors) | Multi-vector unsigned by signed integer dot-product |
| USDOT (by element) | Dot product with unsigned and signed integers (vector, by element) |
| USDOT (indexed) | Unsigned by signed 8-bit integer indexed dot product to 32-bit integer |
| USDOT (vector) | Dot product with unsigned and signed integers (vector) |
| USDOT (vectors) | Unsigned by signed 8-bit integer dot product to 32-bit integer |
| USHL | Unsigned shift left (register) |
| USHLL, USHLL2 | Unsigned shift left long (immediate) |
| USHLLB | Unsigned shift left long by immediate (bottom) |
| USHLLT | Unsigned shift left long by immediate (top) |
| USHR | Unsigned shift right (immediate) |
| USMLALL (multiple and indexed vector) | Multi-vector unsigned by signed integer multiply-add long-long by indexed element |
| USMLALL (multiple and single vector) | Multi-vector unsigned by signed integer multiply-add long-long by vector |
| USMLALL (multiple vectors) | Multi-vector unsigned by signed integer multiply-add long-long |
| USMMLA | Unsigned by signed 8-bit integer matrix multiply-accumulate to 32-bit integer |
| USMMLA (vector) | Unsigned and signed 8-bit integer matrix multiply-accumulate (vector) |
| USMOP4A | Unsigned by signed integer quarter-tile sums of four outer products, accumulating |
| USMOP4S | Unsigned by signed integer quarter-tile sums of four outer products, subtracting |
| USMOPA (4-way) | Unsigned by signed integer sum of outer products and accumulate |
| USMOPS | Unsigned by signed integer sum of outer products and subtract |
| USQADD | Unsigned saturating addition of signed value |
| USQADD | Unsigned saturating accumulate of signed value |
| USRA | Unsigned shift right and accumulate (immediate) |
| USRA | Unsigned shift right and accumulate (immediate) |
| USTMOPA | Unsigned by signed integer sparse sum of four outer products, accumulating |
| USUBL, USUBL2 | Unsigned subtract long |
| USUBLB | Unsigned subtract long (bottom) |
| USUBLT | Unsigned subtract long (top) |
| USUBW, USUBW2 | Unsigned subtract wide |
| USUBWB | Unsigned subtract wide (bottom) |
| USUBWT | Unsigned subtract wide (top) |
| USVDOT | Multi-vector unsigned by signed integer vertical dot-product by indexed element |
| UTMOPA (2-way) | Unsigned integer sparse sum of two outer products, accumulating |
| UTMOPA (4-way) | Unsigned integer sparse sum of four outer products, accumulating |
| UUNPK | Unpack and zero-extend multi-vector elements |
| UUNPKHI, UUNPKLO | Unsigned unpack and extend half of vector |
| UVDOT (2-way) | Multi-vector unsigned integer vertical dot-product by indexed element |
| UVDOT (4-way) | Multi-vector unsigned integer vertical dot-product by indexed element |
| UXTB | Unsigned extend byte |
| UXTB, UXTH, UXTW | Unsigned byte / halfword / word extend (predicated) |
| UXTH | Unsigned extend halfword |
| UXTL, UXTL2 | Unsigned extend long |
| UZP (four registers) | Concatenate elements from four vectors |
| UZP (two registers) | Concatenate elements from two vectors |
| UZP1 | Unzip vectors (primary) |
| UZP1, UZP2 (predicates) | Concatenate even or odd elements from two predicates |
| UZP1, UZP2 (vectors) | Concatenate even or odd elements from two vectors |
| UZP2 | Unzip vectors (secondary) |
| UZPQ1 | Concatenate even elements within each pair of quadword vector segments |
| UZPQ2 | Concatenate odd elements within each pair of quadword vector segments |
| WFE | Wait for event |
| WFET | Wait for event with timeout |
| WFI | Wait for interrupt |
| WFIT | Wait for interrupt with timeout |
| WHILEGE (predicate as counter) | While decrementing signed scalar greater than or equal to scalar (predicate-as-counter) |
| WHILEGE (predicate pair) | While decrementing signed scalar greater than or equal to scalar (pair of predicates) |
| WHILEGE (predicate) | While decrementing signed scalar greater than or equal to scalar |
| WHILEGT (predicate as counter) | While decrementing signed scalar greater than scalar (predicate-as-counter) |
| WHILEGT (predicate pair) | While decrementing signed scalar greater than scalar (pair of predicates) |
| WHILEGT (predicate) | While decrementing signed scalar greater than scalar |
| WHILEHI (predicate as counter) | While decrementing unsigned scalar higher than scalar (predicate-as-counter) |
| WHILEHI (predicate pair) | While decrementing unsigned scalar higher than scalar (pair of predicates) |
| WHILEHI (predicate) | While decrementing unsigned scalar higher than scalar |
| WHILEHS (predicate as counter) | While decrementing unsigned scalar higher or same as scalar (predicate-as-counter) |
| WHILEHS (predicate pair) | While decrementing unsigned scalar higher or same as scalar (pair of predicates) |
| WHILEHS (predicate) | While decrementing unsigned scalar higher or same as scalar |
| WHILELE (predicate as counter) | While incrementing signed scalar less than or equal to scalar (predicate-as-counter) |
| WHILELE (predicate pair) | While incrementing signed scalar less than or equal to scalar (pair of predicates) |
| WHILELE (predicate) | While incrementing signed scalar less than or equal to scalar |
| WHILELO (predicate as counter) | While incrementing unsigned scalar lower than scalar (predicate-as-counter) |
| WHILELO (predicate pair) | While incrementing unsigned scalar lower than scalar (pair of predicates) |
| WHILELO (predicate) | While incrementing unsigned scalar lower than scalar |
| WHILELS (predicate as counter) | While incrementing unsigned scalar lower or same as scalar (predicate-as-counter) |
| WHILELS (predicate pair) | While incrementing unsigned scalar lower or same as scalar (pair of predicates) |
| WHILELS (predicate) | While incrementing unsigned scalar lower or same as scalar |
| WHILELT (predicate as counter) | While incrementing signed scalar less than scalar (predicate-as-counter) |
| WHILELT (predicate pair) | While incrementing signed scalar less than scalar (pair of predicates) |
| WHILELT (predicate) | While incrementing signed scalar less than scalar |
| WHILERW | While free of read-after-write conflicts |
| WHILEWR | While free of write-after-read/write conflicts |
| WRFFR | Write the first-fault register |
| XAFLAG | Convert floating-point condition flags from external format to Arm format |
| XAR | Bitwise exclusive-OR and rotate right by immediate |
| XAR | Exclusive-OR and rotate |
| XPACD, XPACI, XPACLRI | Strip Pointer Authentication Code |
| XTN, XTN2 | Extract narrow |
| YIELD | Yield |
| ZERO (double-vector) | Zero ZA double-vector groups |
| ZERO (quad-vector) | Zero ZA quad-vector groups |
| ZERO (single-vector) | Zero ZA single-vector groups |
| ZERO (table) | Zero ZT0 |
| ZERO (tiles) | Zero a list of 64-bit element ZA tiles |
| ZIP (four registers) | Interleave elements from four vectors |
| ZIP (two registers) | Interleave elements from two vectors |
| ZIP1 | Zip vectors (primary) |
| ZIP1, ZIP2 (predicates) | Interleave elements from two half predicates |
| ZIP1, ZIP2 (vectors) | Interleave elements from two half vectors |
| ZIP2 | Zip vectors (secondary) |
| ZIPQ1 | Interleave elements from low halves of each pair of quadword vector segments |
| ZIPQ2 | Interleave elements from high halves of each pair of quadword vector segments |
.png)
4 months ago
11
