Intel's Nova Lake-Ax for Local LLMs – What We Know About AMD's Halo Competitor

For local LLM enthusiasts, the hardware landscape is in constant motion. We are always searching for the next breakthrough that delivers more VRAM and memory bandwidth for our dollar. While multi-GPU setups using used server cards have been the go-to solution, a new class of powerful APUs, or “big APUs,” is emerging. AMD fired the first major shot with Strix Halo, and now, rumors point to Intel’s potential answer: a powerful chip codenamed Nova Lake-AX. Let’s break down what we know and what it could mean for running large models locally.

Decoding the Nova Lake-AX Rumors

Recent leaks, primarily from credible sources like Raichu, have painted a picture of an ambitious design from Intel. Nova Lake-AX appears to be an APU built to compete at the highest level. The rumored specifications suggest a chiplet-based design with a significant focus on both CPU and integrated GPU performance.

The CPU side is rumored to feature a combination of 8 P-Cores, 16 E-Cores, and 4 LP-Cores for a total of 28 cores. While impressive, our main interest lies in the integrated graphics and memory subsystem. The GPU is said to be based on the unreleased Xe3P architecture, packing a massive 384 Execution Units (EUs). For context, this is more than double the EU count of a discrete Arc B580 desktop GPU.

Most critically for LLM inference, Nova Lake-AX is rumored to feature a wide 256-bit memory bus. This is the same width as AMD’s Strix Halo, but Intel aims to pair it with much faster LPDDR5X memory, potentially running at speeds of 9600 MT/s or even 10667 MT/s. However, it’s crucial to approach this information with caution. Leakers have also indicated that the project’s future is uncertain, and it may not ever reach production.

Nova Lake-AX vs. Strix Halo for LLM Inference

When we place the rumored specs of Nova Lake-AX against the known specifications of AMD’s Strix Halo, a clear picture emerges of Intel’s design goals. For LLM users, two metrics matter most: compute power for prompt processing and memory bandwidth for token generation.

On paper, Nova Lake-AX is designed for a decisive advantage in raw compute. Its 384 Xe3P EUs would contain a total of 6,144 FP32 cores, more than double the 2,560 cores found in Strix Halo’s 40 RDNA 3.5 Compute Units. This substantial difference in raw horsepower would theoretically lead to much faster prompt processing, allowing you to feed large contexts to a model with less waiting.

The more significant metric for a smooth local LLM experience is token generation speed, which is almost entirely dependent on memory bandwidth. Here, the competition is closer but still favors Intel. Both chips use a 256-bit memory bus, but Nova Lake-AX’s support for faster memory gives it a critical edge. At 10667 MT/s, Intel’s APU could achieve a theoretical peak memory bandwidth of around 341 GB/s. This is a substantial 33% increase over Strix Halo’s 256 GB/s, which is limited by its 8000 MT/s memory. For anyone who has experienced the slow token-by-token output of a memory-bottlenecked model, that 33% uplift is a game-changer.

On-Paper Specification Comparison

Here is a direct comparison based on current rumors and known facts.

The Medusa Halo Complication

Timing is everything in the hardware world. While Nova Lake-AX looks impressive against Strix Halo, it is not expected to launch until 2027, if at all. By that time, AMD will have moved on to its next-generation APU, codenamed Medusa Halo.

Leaks about Medusa Halo suggest it will directly address the primary limitation of Strix Halo: memory bandwidth. It is expected to move to a much wider 384-bit memory bus and support next-generation LPDDR6 memory. This combination could push its memory bandwidth into the 480 GB/s to 690 GB/s range, leapfrogging the rumored capabilities of Nova Lake-AX. If Intel’s chip arrives in 2026, it will find itself competing with a much more formidable opponent.

Final Thoughts: On-Paper Potential vs. Practical Reality

On paper, Intel’s Nova Lake-AX is being designed to be a monster. It aims for more than double the raw computational power and a significant memory bandwidth advantage over AMD’s Strix Halo. For the local LLM enthusiast, this combination promises faster prompt processing and quicker token generation in a single, power-efficient package.

However, raw horsepower is only part of the story. The real-world performance will depend on factors beyond a spec sheet. The efficiency of the Xe3 architecture, its ability to manage thousands of threads for AI workloads, and the maturity of Intel’s software drivers will be critical. AMD has a head start with its ROCm software stack on APUs, and Intel will need a robust and optimized software ecosystem to compete.

For now, Nova Lake-AX remains an exciting but uncertain prospect. It shows that Intel recognizes the growing market for high-performance APUs. While we wait for concrete details, AMD’s Strix Halo is a real product. The brewing competition between these chip giants is excellent news for us, as it promises to bring more powerful and efficient hardware for running ever-larger language models on our local machines.