Penn State boffins create silicon-free two-dimensional computer

Gaze into the temporal distance and you might spot the end of the age of silicon looming somewhere out there, as a research team at Penn State University claims to have built the first working CMOS computer entirely from two-dimensional materials.

The team, led by Pennsylvania State University engineering science professor Saptarshi Das, published a paper last week detailing the design and construction of their 2D one instruction set computer (OISC) based on the same complementary metal-oxide-semiconductor (CMOS) design that's a standard part of modern silicon-based computers. OISC is a minimalist abstract machine model that performs all operations using a single, universal instruction.

Does that mean we can expect to live through a post-silicon, 2D computing revolution? It won't be quite like that, Das told us. Rather, 2D CMOS computers will have specialized uses.

"They could become competitive in specialized domains such as edge AI, neuromorphic systems, or flexible electronics," Das told us.

The 2D machine they built is silicon-free, using molybdenum disulfide for n-type and tungsten diselenide for p-type transistors. The material pair "offer complementary electrical characteristics, relatively high mobility, and have demonstrated scalable growth via metal–organic chemical vapor deposition (MOCVD)," Das told The Register in an email. MOCVD was used to fabricate the team's 2D CMOS platform on sapphire wafers, with transistor channels just one atom thick. 

CMOS systems need both n- and p-type transistors (which move electrons along a circuit by having an excess and deficiency of electrons, respectively) to achieve the goal of CMOS computing - energy efficiency and reusability. That's why the team's 2D CMOS design is such a breakthrough, according to Das.

We have demonstrated, for the first time, a CMOS computer built entirely from 2D materials

"We have demonstrated, for the first time, a CMOS computer built entirely from 2D materials," Das said in an announcement on the Penn State website.

That's not to say Das' system is fast, mind you. According to the research paper, the Penn State team only managed to achieve an operating frequency of up to 25 kHz at supply voltages below 3 V. This speed was limited primarily by parasitic capacitance - unwanted capacitance between closely spaced circuit elements that impairs switching performance.

While parasitic capacitance is a problem now, Das told us his team is working on solving that issue now. According to the team's simulations, if the parasitic capacitance issue is resolved, "2D-CMOS logic gates could achieve delays as low as 200 [picoseconds], equivalent to operating frequencies of ~5 GHz." 

Is a 2D computing future coming soon?

With a proof-of-concept built and tested, the next obvious question is whether such a system could be scaled up. Das thinks so.

"[Scalability] is one of the most critical aspects of our work," Das told us. "While some steps (e.g., layer alignment and transfer) are still manual, most of the process is compatible with industry tools and can be automated."

The team fabricated more than 2,000 transistors on a 2-inch sapphire wafer, achieving a 95 percent functional yield, Das told us. He expects the project to be able to scale up without much issue, provided they can automate the rest of those processes. 

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The test chip was also stable, Das said, with the circuit showing "robust functionality under ambient conditions over the course of repeated measurements." Long-term reliability studies, which will include bias stress, temperature cycling and radiation tolerance, are part of the next phase of development, he told us. 

Along with that testing and work to reduce parasitic capacitance, Das said his team is now working to expand instruction sets and memory complexity to enable the creation of more powerful processors, scaling down gate lengths to increase performance and integrating new gate dielectrics. Work to make this practical is ongoing, in other words. ®